High-Precision, Mixed-Signal Mismatch Measurement of Metal–Oxide–Metal Capacitors

Bustamante, Danilo; Janke, Devon; Swindlehurst, Eric; Chiang, Shiuh–hua Wood

doi:10.1109/tcsii.2016.2642820

Cited by 7 publications

(1 citation statement)

References 8 publications

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“…From the confined areas shown in the plot, it becomes evident that an accurate BEOL fabrication process is required for highprecision analog computing. Advanced patterning techniques in deep submicron nodes allow to keep the mismatch below 0.05%, even for small C unit sizes [24]. Furthermore, matching will gradually improve in upcoming technologies since the metal fabrication precision is increasing as the transistors are shrinking in accordance with Moore's law [25], [26].…”

Section: F Noise and Mismatch Impactmentioning

confidence: 99%

An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power

Khaddam-Aljameh

Francese

Benini

et al. 2021

IEEE Trans. VLSI Syst.

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Section: F Noise and Mismatch Impactmentioning

confidence: 99%

An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power

Khaddam-Aljameh

Francese

Benini

et al. 2021

IEEE Trans. VLSI Syst.

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High-quality-factor flexible and transparent capacitors with Cr–Au nanomeshes as bottom electrodes

Guo

Zhang

et al. 2019

Nanotechnology

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Flexible and transparent capacitors have been fabricated on polyethylene naphthalate (PEN) substrates. The Cr–Au nanomeshes, ZrO2, and aluminum-doped zinc oxide (AZO) films were prepared in sequence as bottom electrodes, dielectric layers and top electrodes. A high quality factor of 82 was obtained, nearly 4.9 times larger than that ever reported, which directly indicates much lower power consumption. The flexible capacitors can normally work at a bending radius of 7 mm without any loss of electrical performance, and even maintain electrical characteristics after cyclical bending tests. Moreover, a high capacitance density of 12.3 fF μm−2 and an ultralow leakage current of 1.5 × 10−8 A cm−2 at 1 V have been achieved. Transmittance measurements indicate that the capacitors represent an average optical transmittance of over 50% at a visible region. This is, therefore, a dramatic step toward real applications in flexible and transparent integrated circuits.

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A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS

Yao

et al. 2021

IEEE Access

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This paper reports a 12-bit 100-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for low-power wireless and imaging systems. A split-capacitor digitalto-analog converter (CDAC) structure is adopted for reducing the core area and improving the sampling speed. The linearity of the CDAC is calibrated by programming the least-significant-bits (LSBs) capacitor. The unit capacitor in the CDAC array is customized for higher symmetry and reducing their mismatch. Our SAR ADC is based on asynchronous logic, and its timing is controlled by a delaying block in the critical path. The prototype is fabricated in a 65-nm CMOS process with a 1.2 V supply and occupies an active area of 0.029 mm 2 . With a 100-MS/s sampling rate, the measured ENOB scores 10.17 bits for 1.5-MHz input with a figure-of-merit (FoM) of 6.94 fJ/conversion-step. It can achieve 8.83 bits for the Nyquist input signal.INDEX TERMS Successive approximation register (SAR) analog-to-digital converter (ADC), CMOS, split-CDAC, customized unit capacitor, asynchronous logic, figure-of-merit (FoM).

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High-Precision, Mixed-Signal Mismatch Measurement of Metal–Oxide–Metal Capacitors

Cited by 7 publications

References 8 publications

An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power

An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power

High-quality-factor flexible and transparent capacitors with Cr–Au nanomeshes as bottom electrodes

A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS

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