High sampling rate retimed DLMS filter implementations in Virtex-II FPGA

Yi, Yang; Woods, Roger; Ting, Lok-Kee; Cowna, C.F.N.

doi:10.1109/sips.2002.1049699

Cited by 9 publications

(3 citation statements)

References 5 publications

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“…14, where , , and are the latencies of pre-characterized adder, multiplier, and multiplexer blocks, respectively. This extends the retiming algorithm from [25] that assumes equal latency in add and multiply blocks, as applied to FIR filters. Starting from the DFG representation, the latency assignment is carried out as follows.…”

Section: ) Loop Retimingmentioning

confidence: 96%

Power and Area Minimization for Multidimensional Signal Processing

Marković

Nikolić

Brodersen

2007

IEEE J. Solid-State Circuits

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Abstract-Sensitivity-based methodology is applied to optimization of performance, power and area across several levels of design abstraction for a complex wireless baseband signal processing algorithm. The design framework is based on a unified, block-based graphical description of the algorithm to avoid design re-entry in various phases of chip development. The use of architectural techniques for minimization of power and area for complex signal processing algorithms is demonstrated using this framework. As a proof of concept, an ASIC realization of the MIMO baseband signal processing for a multi-antenna WLAN is described. The chip implements a 4 4 adaptive singular value decomposition (SVD) algorithm with combined power and area minimization achieving a power efficiency of 2.1 GOPS/mW (12-bit add equivalent) in just 3.5 mm 2 in a standard 90 nm CMOS process. The computational throughput of 70 GOPS is implemented with 0.5 M cells at a 100 MHz clock and 385 mV supply, dissipating 34 mW of power. With optimal channel conditions the algorithm implemented can deliver up to 250 Mb/s over 16 sub-carriers.

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Section: ) Loop Retimingmentioning

confidence: 96%

Power and Area Minimization for Multidimensional Signal Processing

Marković

Nikolić

Brodersen

2007

IEEE J. Solid-State Circuits

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“…For a given throughput constraint, the solution of Eq. (2) is a set of positive integers (m, a, u) that corresponds to equal clock period, adding b 1 and b 2 balancing registers as needed to satisfy loop latency N. Accounting for different latency of library blocks nicely extends the retiming algorithm from [5].…”

Section: Loop Retimingmentioning

confidence: 99%

Power and Area Efficient VLSI Architectures for Communication Signal Processing

Marković

Nikolić

Brodersen

2006

2006 IEEE International Conference on Communications

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Abstract-A methodology for VLSI realization of signal processing algorithms for wireless communications is presented that optimizes architecture for reduced power and area. When power is limited, optimal architecture represents a point on the best power-area tradeoff curve that is obtained by balancing the algorithm throughput with the power-performance tradeoff of the underlying building blocks. Architectural optimization is done in the graphical Matlab/Simulink environment, which is also used for algorithm verification. Hardware description language produced by Simulink enables algorithm emulation on the FPGA and also serves as design entry for the chip realization. This is illustrated on complex multi-dimensional algorithms such as wideband MIMO channel decoupling through singular value decomposition (SVD) using 16 sub-carriers.

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“…Throughput and resource usage constraints are placed on the FPGA processor by the system in which it is to be integrated, and a clever design methodology is required which rapidly explores the throughput/resource usage tradeoff to efficiently exploit the FPGA resources for the required throughput requirement. Techniques, such as retiming, for folding and unfolding transformations 6 explore this trade-off and can produce highly efficient results 7 Current approaches in this arena 8 perform architectural retiming techniques for graphs where the folding transformation has been defined. They provide little insight into the effect of the mapping stage from SFG to circuit architecture.…”

Section: Introductionmentioning

confidence: 99%

Design technologies for DSP algorithm implementation on heterogeneous architectures

et al. 2003

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Computationally intensive digital signal processing (DSP) systems sometimes have real time requirements beyond that which programmable processor platform solutions, consisting of RISC and DSP processors, can achieve. The addition of Field Programmable Gate Array (FPGA) components to these platforms provides a configurable hardware resource where increased parallelism levels allow very large computational rates. Techniques to implement circuit architectures from signal flow graph (SFG) algorithm expression can produce highly efficient processor implementations. Applying folding transformations produces implementations where hardware resource usage is reduced at the possible expense of throughput. In this paper a new development methodology is presented which analyses the SFG algorithm to suggest appropriate folding techniques. By characterizing different folding techniques, a template circuit architecture can be created early in the design process which does not alter throughout the remainder of the implementation process. Retiming techniques applied to the algorithm SFG produces the properly timed implementation from the template. By applying this methodology, architectural exploration can be quickly and efficiently performed to generate a set of implementations (an 'implementation space') to best meet the constraints of the system. When applied to a Normalised Lattice Filter design example, the results demonstrate high savings on FPGA resource usage, with little reduction in real time performance, demonstrating the implementation advantage of employing this methodology.

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High sampling rate retimed DLMS filter implementations in Virtex-II FPGA

Cited by 9 publications

References 5 publications

Power and Area Minimization for Multidimensional Signal Processing

Power and Area Minimization for Multidimensional Signal Processing

Power and Area Efficient VLSI Architectures for Communication Signal Processing

Design technologies for DSP algorithm implementation on heterogeneous architectures

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