High speed 0.1 μm dual gate CMOS with low energy phosphorus/boron implantation and cobalt salicide

Abstract

A novel dual gate CMOS with low energy phosphorus/boron implantation and cobalt salicide is proposed. This technology suppresses boron penetration for PMOS, while maintaining high current drivability for nMOS with simple process steps. In addition, the drain junction capacitance of nMOS is drastically decreased, compared to a conventional MOSFET with arsenic sourcddmin. The delay time of CMOS ring oscillator was 28 psec, which is due to low junction capacitance and high current driving capability. (a) Extension Arsenic lOkeV BF2 1OkeV $ 4 + $ . n n I \ I p-well n-well Introduction(b) Pre-amorphization Dual gate CMOS is a key technology to realize high performance MOS devices, because of its strong immunity to short channel effect. However, this technology has trade-offs between depletion effect of n+ gate of nMOS and boron penetration from p+ gate of PMOS. Much attention has been focused on fabrication technology and novel