2006
DOI: 10.1109/ted.2006.882393
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Implant-free high-mobility flatband MOSFET: principles of operation

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Cited by 43 publications
(21 citation statements)
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“…Possible alternatives include Ge, GaAs, InGaAs, InAs, InSb, GaN, and perhaps others [2][3][4][5][6][7][8]. Recently published results from high performance flatband-mode [9] In 0.3 Ga 0.7 As channel enhancement-mode MOSFETs on GaAs substrate conclusively demonstrate that the historical issue of Fermi-level pinning at the GaAs/dielectric interface can be overcome [10]. Although In 0.3 Ga 0.7 As n-channel MOSFETs are well suited to mobile RF applications, technological issues and intrinsic properties limit their ability to challenge aggressively scaled silicon nMOS devices for digital applications.…”
mentioning
confidence: 99%
“…Possible alternatives include Ge, GaAs, InGaAs, InAs, InSb, GaN, and perhaps others [2][3][4][5][6][7][8]. Recently published results from high performance flatband-mode [9] In 0.3 Ga 0.7 As channel enhancement-mode MOSFETs on GaAs substrate conclusively demonstrate that the historical issue of Fermi-level pinning at the GaAs/dielectric interface can be overcome [10]. Although In 0.3 Ga 0.7 As n-channel MOSFETs are well suited to mobile RF applications, technological issues and intrinsic properties limit their ability to challenge aggressively scaled silicon nMOS devices for digital applications.…”
mentioning
confidence: 99%
“…The III-V MOSFETs of this work use the "implant-free" architecture [7] shown schematically in Fig 1. The structure contains a modulation-doped, high mobility channel, surrounded by larger bandgap barriers. The carriers are thus well confined, providing charge control within the channel comparable to that achieved in ultra-thin body SOI MOSFETs.…”
Section: Methodsmentioning
confidence: 99%
“…In the past, the ability to reap the benefits of the high mobility III-V system for n-MOS applications has been hampered by the lack of a device quality gate oxide [4,5]. Recent work utilizing an MBE grown Ga 2 O 3 /(Ga x Gd 1-x ) 2 O 3 dielectric stack (GGO) on GaAs however has demonstrated interface state densities sufficiently low to unpin the Fermi level at the oxide/semiconductor interface [6][7][8]. This gate stack technology, in conjunction with a suitably engineered underlying III-V layer structure, can be combined to realise enhancement mode III-V MOSFETs.…”
Section: Introductionmentioning
confidence: 99%
“…The design and particularly the vertical device architecture have to be optimized with respect to the channel material and its orientation bearing in mind that at small channel thicknesses the mobility is degraded due to enhanced scattering of carriers with confined phonons [14]. One such recently proposed new device concept which does not require implanted source/drain regions and extensions is the enhancement mode implant free MOSFET [15], [16] illustrated in Fig. 1.…”
Section: Introductionmentioning
confidence: 99%