Improved performance of IBM Enterprise System/9000 bipolar logic chips

Brown, Alan; Eckhardt, J.P.; Mayo, M.; Svarczkopf, W. A.; Gaur, S.P.

doi:10.1147/rd.365.0829

Cited by 9 publications

(5 citation statements)

References 6 publications

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“…To explore the design space, several design choices (multicore versus C-slow, optimal number of cores and hardware thread contexts, and optimal frequency and supply voltage) are evaluated for both the CMOS and the MCML. 5 Note that the best design choice for the static CMOS is multicore instead of C-slow, while the opposite is true for MCML. As listed in Table VI, a C-slow (C = 1, 2, 4, 8), a single-core MCML processor is compared with a 2 GHz C-core CMOS (0.8 V) processor.…”

Section: Architecturementioning

confidence: 99%

“…MCML is the CMOS successor of bipolar emitter-coupled logic (ECL), which has been used in high-speed applications since the 1970s. The Cray-1 [4], the IBM Enterprise System/9000 [5], and the IBM System/390 [6] all used ECL and differential current switching to achieve high speeds with low noise. 1 The low-noise environment has allowed the Cray-1 to use an entirely unregulated power supply [7].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS

Bai

Song

Bojnordi

et al. 2016

IEEE Trans. VLSI Syst.

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This paper explores the use of MOS current-mode logic (MCML) as a fast and low noise alternative to static CMOS circuits in microprocessors, thereby improving the performance, energy efficiency, and signal integrity of future computer systems. The power and ground noise generated by an MCML circuit is typically 10-100× smaller than the noise generated by a static CMOS circuit. Unlike static CMOS, whose dominant dynamic power is proportional to the frequency, MCML circuits dissipate a constant power independent of clock frequency. Although these traits make MCML highly energy efficient when operating at high speeds, the constant static power of MCML poses a challenge for a microarchitecture that operates at the modest clock rate and with a low activity factor. To address this challenge, a single-core microarchitecture for MCML is explored that exploits the C-slow retiming technique, and operates at a high frequency with low complexity to save energy. This design principle contrasts with the contemporary multicore design paradigm for static CMOS that relies on a large number of gates operating in parallel at the modest speeds. The proposed architecture generates 10-40× lower power and ground noise, and operates within 13% of the performance (i.e., 1/ExecutionTime) of a conventional, eight-core static CMOS processor while exhibiting 1.6× lower energy and 9% less area. Moreover, the operation of an MCML processor is robust under both systematic and random variations in transistor threshold voltage and effective channel length.Index Terms-Architecture-circuit codesign, energy efficient, low noise, microprocessors, MOS current-mode logic (MCML). 1063-8210

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Section: Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS

Bai

Song

Bojnordi

et al. 2016

IEEE Trans. VLSI Syst.

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“…By routing a signal and its complement in adjacent tracks throughout their run from source to terminus, the ability to reject common mode noise is enhanced. Digital Equipment's new macropipe-lined VAX and IBM's 9000 and AS400 now employ differential signals on critical nets and clock distribution signals [1,2,3]. However, differential routing is not without costs.…”

Section: A Motivationmentioning

confidence: 99%

“…formulated using exhaustive search. It explores all possible via settings and terminates with one of two outcomes: (1) successful bifurcation, or (2) realization that the net is not bifurcatable. Either of these cases may entail exponential running time as a function of vias in the net.…”

Section: (C) This Is Possiblementioning

confidence: 99%

Optimal Differential Routing based on Finite StateMachine Theory

1997

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Noise margins in high speed digital systems continue to erode. Full differential signal routing provides a mechanism for deferring these effects. This paper proposes a three stage routing process for solving the adjacent placement routing problem of differential signal pairs, and proves that it is optimal. The process views differential pairs as logical nets; routes the logical nets; then bifurcates the result to achieve a physical realization. Finite state machine theory provides the critical theoretical underpinning and formal proof of correctness necessary for linear time bifurcation. Regular expressions map the theoretical solution to an appropriate implementation strategy that employs feature vectors for net recognition.

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“…The CML circuits have a loaded gate delay of 25 ps. The three-level current switch stacking gives access to high-functionality gates and helps offset the area penalty from the different(ia1 wiring [3].…”

Section: Technologymentioning

confidence: 99%

A 500 ps 32 × 8 register file implemented in GaAs/AlGaAs HBTs [F-RISC/G processor]

Nah

Philhower²,

Greub³

et al.

15th Annual GaAs IC Symposium

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A high speed register file has been designed that is wellsuited for achieving the speed potential of a fast but yieldlimited technology such a5 GaAs/AlGaAs HBT. Descriptions of address driver, write, and threshold voltage generator circuits developed are presented. The test strategy utilizes two Linear Feedback Shift, Registers (LFSRs) to provide address and data patterns to the register file. A match circuit verifies valid memory function and indicates read access time. The test results indicaie a read access time of 500 ps.

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Improved performance of IBM Enterprise System/9000 bipolar logic chips

Cited by 9 publications

References 6 publications

Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS

Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS

Optimal Differential Routing based on Finite StateMachine Theory

A 500 ps 32 × 8 register file implemented in GaAs/AlGaAs HBTs [F-RISC/G processor]

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