In-depth analysis of electrical characteristics for polycrystalline silicon vertical thin film transistors

Abstract

A polycrystalline silicon vertical thin film transistor (VTFT) is fabricated, and the electrical parameters are extracted and compared with the typical lateral thin film transistor (LTFT). The similar subthreshold slope and the distinct field effect mobility is verified by the DOS calculation in the deep and shallow trap regions, respectively, and in this article, it is used to compare with the grain boundary trap density at a lower V ds =10 mV that eliminates the velocity saturation effect. The accurate threshold voltage is also calculated by a systematic model including the grain boundary barrier modulation effect. A pseudo-subthreshold region is demonstrated, and the threshold voltage exactly corresponds to the 3kT point of the grain boundary barrier. The low field effect mobility of VTFT is mainly due to the small grain size and also slightly affected by the parasitic resistance, which can be improved by optimizing the processing conditions, especially by improving the sidewalls smoothness and the active layer quality.

Elucidation of the Density of States for Polycrystalline Silicon Vertical Thin-Film Transistors

“…Therefore, the only unsolved parameter is the grain boundary barrier height b at the flatband state, which can be solved as follows. In another reference paper [18], the grain boundary barrier height b can be elucidated as follows:…”

“…For the intrinsic mobility of μ 0 , when without considering surface scattering and the grain boundary barrier modulation parameter, it can be deduced from the ln(μ eff )−(−1)/(V gs -V t ) relationship [18], as shown in Fig. 4(a).…”