Instruction scheduling for instruction level parallel processors

Faraboschi, Paolo; Fisher, Joseph A.; Young, Cliff

doi:10.1109/5.964443

Cited by 60 publications

(49 citation statements)

References 62 publications

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“…CASTED works on tightly coupled cores such as RAW [32], VOLTRON [37] and VLIW clusters [8]. In this work, we use a clustered VLIW architecture with configurable resources and inter-cluster communication latency (Fig.…”

Section: A Target Architecturementioning

confidence: 99%

“…These architectures look like Fig.1. They are wide-issue scalable clustered architectures (such as [8], [32], [37]). Such architectures differ from traditional monolithic (non-clustered) designs in that critical resources (e.g the register file) are partitioned into small parts.…”

Section: A Error Detection Overheadmentioning

confidence: 99%

“…The proposed software-based error detection methodology takes advantage of the features (such as fast inter-core communication) of scalable tightly coupled cores [8][32] [37] to optimally distribute the error detection overhead across cores/clusters while maintaining high reliability. In the text, we use the terms cluster and core interchangeably as the proposed technique can apply to architectures with tightlycoupled cores or to clustered VLIWs.…”

Section: Introductionmentioning

confidence: 99%

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CASTED: Core-Adaptive Software Transient Error Detection for Tightly Coupled Cores

Mitropoulou

Porpodas

Cintra

2013

2013 IEEE 27th International Symposium on Parallel and Distributed Processing

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Abstract-Aggressive silicon process scaling over the last years has made transistors faster and less power consuming. Meanwhile, transistors have become more susceptible to errors. The need to maintain high reliability has led to the development of various software-based error detection methodologies which target either single-core or multi-core processors.In this work, we present CASTED, a Core-Adaptive Software Transient Error Detection methodology that focuses on improving the impact of error detection overhead on singlechip scalable architectures that are composed of tightly coupled cores. The proposed compiler methodology adaptively distributes the error detection overhead to the available resources across multiple cores, fully exploiting the abundant ILP of these architectures. CASTED adapts to a wide range of architecture configurations (issue-width, inter-core delay).We evaluate our technique on a range of architecture configurations using the MediabenchII video and SPEC CINT2000 benchmark suites. Our approach successfully adapts to (and regularly outperforms by up to 21.2%) the best fixed state-ofthe-art approach while maintaining the same fault coverage.

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Section: A Target Architecturementioning

confidence: 99%

Section: A Error Detection Overheadmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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CASTED: Core-Adaptive Software Transient Error Detection for Tightly Coupled Cores

Mitropoulou

Porpodas

Cintra

2013

2013 IEEE 27th International Symposium on Parallel and Distributed Processing

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“…Our approach can be easily incorporated into any of existing list scheduling like algorithms [3,4,5].…”

Section: Introductionmentioning

confidence: 99%

Operation scheduling for the synthesis of false loop free circuits

Huang

Cheng

2007

IEICE Electron. Express

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If resource constraints are specified, the false loop free circuit must be built during the scheduling phase. Although the previous approach guarantees to have a false loop free circuit mapping, it does not attempt to minimize the number of control steps. In this paper, we present an effective approach to find a scheduled code, which not only guarantees to have a false loop free circuit mapping but also to minimize the number of control steps. Experimental results show that our approach achieves good results in terms of the number of control steps.

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“…In current Very long Instruction Word (VLIW) architectures, exploiting high amounts of latent Instruction Level Parallelism (ILP) may be a very difficult task [4], because the degree of ILP is mainly limited by the number of functional units that can work simultaneously when they are connected to a single register file.…”

Section: Introductionmentioning

confidence: 99%

Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications

Barretta

Fornaciari

Sami

et al.

Design, Automation and Test in Europe

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Instruction scheduling for instruction level parallel processors

Abstract: Nearly all personal computer and workstation processors, and virtually all high-performance embedded processor cores, now embody instruction level parallel (ILP)

Cited by 60 publications

References 62 publications

CASTED: Core-Adaptive Software Transient Error Detection for Tightly Coupled Cores

CASTED: Core-Adaptive Software Transient Error Detection for Tightly Coupled Cores

Operation scheduling for the synthesis of false loop free circuits

Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications

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