Integrable Quasivertical GaN U‐Shaped Trench‐Gate Metal‐Oxide‐Semiconductor Field‐Effect Transistors for Power and Optoelectronic Integrated Circuits

Abstract

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On the Conduction Properties of Vertical GaN n-Channel Trench MISFETs

“…A substantial observation is that, for all substrate types, devices with a gate trench etched parallel to the non-polar a-plane exhibits more drain current and a higher electron concentration in the inversion channel than devices with perpendicular layout design with gate trench etched parallel to the non-polar m-plane. This observation stands in contradiction to recent reports on crystal-orientation dependent device characteristics [8][34][9][14] [21][33] [34].…”

Fabrication of Semi-Polar (11-22) GaN V-Groove MOSFET Using Wet Etching Trench Opening Technique

“…AN and its related materials have great potential in the field of power electronics and light-emitting diodes (LEDs). Recent demonstrations of monolithic integration of cplane GaN LEDs with vertical GaN transistors could provide a path for ultra-compact display applications such as virtual reality and augmented reality [1][2][3][4][5][6][7][8][9]. However, c-plane (0001) GaN materials has fundamental limitations: 1) for the LED, it is challenging to achieve a high quantum efficiency due to the quantum-confined stark effect and to incorporate a high indium content in the quantum wells for long wavelength emissions [10], [11].…”

GaN quasi-vertical trench MOSFETs grown on Si substrate with ON-current exceeding 1 A

“…Compared with the single-trench device (normalized by active area), the large-area device (normalized by total device area) presents a higher R ON,sp and a lower I D,max , which can be attributed to: (1) the current crowding effect 27) in quasi-vertical device design; (2) yet-to-be-increased channel density (could be increased by employing hexagonal layout and decreasing the cell pitch). 11,12,28) Figure 5(d) presents the OFF-state performance of this large-area device, presenting a V BR (hard breakdown) of 205 V. Compared with the single-trench device, the largearea device presents a lower V BR , which can be explained by the increased number of dislocations (under the MOS area) 29) and the non-uniformity issue of the TBD and gate dielectric in the large-area device. Figure 5(e) presents the R ON,sp versus V BR benchmarking of the GaN-on-Si trench MOSFETs in this work with other reported GaN vertical transistors.…”

“…[14][15][16][17] For the large-area device, a lower R ON,sp and a higher I D,max can be effectuated by: (1) introducing a thicker bottom n + -GaN layer with higher Si doping to reduce the influence of current crowding in the quasi-vertical design; 27) (2) using fully-vertical GaN-on-Si technique 17) to eliminate the current crowding; (3) employing hexagonal layout and decreasing the cell pitch to increase the channel density. 11,12,28) Lower leakage current and higher V BR can be achieved by: (1) introducing a thicker drift layer with lower Si doping; [11][12][13] (2) optimizing the edge-terminal near the mesa region; 11,12,30) (3) optimizing gate trench etching, gate dielectric deposition and thick bottom dielectric processes to achieve a more stable gate MOS stack; (4) optimizing GaN-on-Si buffers to reduce the dislocation density. 31) Stable gate MOS stack for avoiding drain-togate hard breakdown, combined with high-quality epilayers with low dislocation density and advanced edge-termination techniques [32][33][34] are critical in achieving avalanche capability in GaN-on-Si vertical trench MOSFETs.…”