Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102)
DOI: 10.1109/iitc.1998.704777
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Integration aspects for damascene copper interconnect in low k dielectric

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Cited by 5 publications
(2 citation statements)
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“…This type of failures could originate from Cu CMP process. For example, local regions where scratch defects or under-polished Cu are incurred leaving behind Cu residues in between metal lines [9] will result in a high leakage current and eventually an electrical short failure.…”
Section: Temperature Dependencementioning
confidence: 99%
“…This type of failures could originate from Cu CMP process. For example, local regions where scratch defects or under-polished Cu are incurred leaving behind Cu residues in between metal lines [9] will result in a high leakage current and eventually an electrical short failure.…”
Section: Temperature Dependencementioning
confidence: 99%
“…Cu residues can be found outside the diffusion barrier due to re-sputtered Cu onto the via sidewalls induced during via etching [76]. Cu residues can also be found on the low-k dielectric surface due to micro-scratches, arc-scratches or incomplete CMP polishes [77,78]. An increase in Cu particles at the CMP surface was also found after prolonged exposure to the ambient before cap barrier deposition [79,80].…”
Section: Copper-induced Dielectric Breakdown Modelmentioning
confidence: 99%