Interconnect capacitance, crosstalk, and signal delay for 0.35 μm CMOS technology

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

“…The most important ones are: crosstalk (signal distortion due to cross coupling effects between signals) [1] [2], overshoot (signal rising momentarily above the power supply voltage) [3] [4], reflection (echoing back a portion of a signal), electro-magnetic interference (resulting from the antenna properties) [5], power supply noise [6] and signal skew (delay in arrival time to different receivers) [7] [8].…”

An extraction method to determine interconnect parasitic parameters

“…The effect of gate capacitance of the next stage is not negligible, although its impact may be partially shielded by the loading wire. The quantity is determined by the wire resistance, wire capacitance, and also gate capacitance of the next stage [1], [11], [14] which is identical to the gate capacitance affecting . Among and , the longer one will dominate , and its associated capacitance components will also dominate .…”

“…Results of our method show good agreement with the SEM measurement of dielectric thickness, the numerical simulation [12] of resistance-capacitance correlation, as well as a measured ring oscillator speed with wiring loading across a wafer. The method also has the advantage of consuming much less silicon area than existing methods [3], [10], [14], and is particularly useful in capturing the severe intrawafer dielectric thickness variation in CMP process and the underlying-wire-pitch dependent dielectric thickness in a nonglobal planarized process.…”

“…If the interconnect parasitic parameters can be monitored or extracted during process control monitor (PCM) test right after wafer is fabricated, then these monitored parameters can allow for accurate estimation of interconnect performance [1]- [5], [14] or for backend process improvement, or can provide as a basis for circuit simulation or for circuit failure analysis. Note that here in the case of circuit failure, the failure can be traced back to possibly ill interconnect performance on the same die via the extracted parameter information.…”

“…Major interconnect parameters include wire capacitance and resistance [3]- [5], [13], [14]. Wire capacitance, whether intralayer or interlayer, is determined by dielectric thickness and wire dimension, and wire resistance is determined by wire dimension and wire resistivity.…”