Investigation and Improvement of Verify-Program in Carbon Nanotube-Based Nonvolatile Memory

Ning, Sheyang; Iwasaki, Takaya; Shimomura, Koichiro; Koh, Jung‐Hyuk; Yanagizawa, Eisuke; Rosendale, Glen; Manning, Monte; Viviani, Darlene; Rueckes, Thomas; Takeuchi, Ken

doi:10.1109/ted.2015.2450219

Cited by 16 publications

(8 citation statements)

References 17 publications

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“…Besides individual CNTs, films consisting of many CNTs have also been employed in the fabrication of NEM switches. Networks of CNTs are currently under ongoing research for use in 2T non-volatile memory devices, to date showing good reliability of ≈10 12 non-volatile switching cycles with no observable wear or fatigue and read–write voltages below 5 V [ 123 ]. Here, the switching to the off state is achieved by applying a voltage pulse, presumably causing a phonon heating driven repulsion force [ 123 ].…”

Section: Reviewmentioning

confidence: 99%

Review: Electrostatically actuated nanobeam-based nanoelectromechanical switches – materials solutions and operational conditions

Jasulaneca¹,

Kosmača²,

Meija³

et al. 2018

Beilstein J. Nanotechnol.

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This review summarizes relevant research in the field of electrostatically actuated nanobeam-based nanoelectromechanical (NEM) switches. The main switch architectures and structural elements are briefly described and compared. Investigation methods that allow for exploring coupled electromechanical interactions as well as studies of mechanically or electrically induced effects are covered. An examination of the complex nanocontact behaviour during various stages of the switching cycle is provided. The choice of the switching element and the electrode is addressed from the materials perspective, detailing the benefits and drawbacks for each. An overview of experimentally demonstrated NEM switching devices is provided, and together with their operational parameters, the reliability issues and impact of the operating environment are discussed. Finally, the most common NEM switch failure modes and the physical mechanisms behind them are reviewed and solutions proposed.

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Section: Reviewmentioning

confidence: 99%

Review: Electrostatically actuated nanobeam-based nanoelectromechanical switches – materials solutions and operational conditions

Jasulaneca¹,

Kosmača²,

Meija³

et al. 2018

Beilstein J. Nanotechnol.

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“…7, 8(a), and (b) that the NRAM cell array does not wear-out after 10 8 th write cycle. Moreover, in prior research, the NRAM single cell has demonstrated stable set and reset BERs throughout to 10 12 write cycles [6]. In both memory cell array and single cell measurements, the reset BER is higher than the set BER.…”

Section: Characteristics Of Nram Cell Arraymentioning

confidence: 81%

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

Ning

Iwasaki

Tanakamaru

et al. 2016

IEEE J. Solid-State Circuits

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A novel error correction scheme, called reset-checkreverse-flag (RCRF), is proposed to improve the reliability of storage class memories (SCMs). RCRF divides the conventional Bose-Chaudhuri-Hocquenghem (BCH) code length into multiple subsections. One flag bit is added to each subsection to correct program errors. By reversing the flag bit and user data, at least one reset error in each subsection can be recovered. A 4 Mbit carbon nanotube (CNT) based nano-random access memory (NRAM) cell array is measured to verify this scheme. During 10 8 write cycles, it is demonstrated that RCRF reduces the program bit error rate (BER) by 50% and only requires 0.4% extra array area for the flag bits. Next, BCH ECC is applied after RCRF to correct the remaining errors. Compared with the conventional BCH ECC-only approach, the proposed combination of RCRF and BCH ECC reduces parity overhead by 35% and ECC decoding latency by 16%. Therefore, RCRF is especially suited for read-intensive types of data storage, such as video and audio. On the other hand, for high endurance applications, RCRF and BCH ECC is also effective to improve the cycling reliability of resistive memories, and 50 times endurance extension is demonstrated for a 50 nm Al x O y resistive RAM (ReRAM) test chip.Index Terms-Carbon nanotube, emerging memory, error correcting code, memory controller, non-volatile memory, NRAM, reliability, solid-state drive, storage class memory.

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“…Emerging non-volatile memories, such as nano-random access memory (NRAM), resistive random access memory (ReRAM), and phase-change memory (PRAM) have advantages of fast program, large program endurance, and low program voltage compared with conventional non-volatile memory, such as NAND flash. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18] Different physical mechanisms can be found on these emerging non-volatile memories. In specific, binary data "0" and "1" is stored in ReRAM by switching the cell resistance between high resistance state (HRS) and low resistance state (LRS).…”

Section: Introductionmentioning

confidence: 99%

“…This phenomenon can be explained by using a proposed physical mechanism in Ref. 13. Different amounts of CNT contacts near top and bottom electrodes are responsible for the variation of dominant physical mechanism on set and reset.…”

Section: Introductionmentioning

confidence: 99%

“…Different amounts of CNT contacts near top and bottom electrodes are responsible for the variation of dominant physical mechanism on set and reset. 13) For the detail of NRAM program characteristics, the measurement on NRAM single cell demonstrated >10 12 program endurance and 20 µA program current. 13,14) These characteristics are more advanced than ReRAM and PRAM, as shown in Table I.…”

Section: Introductionmentioning

confidence: 99%

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Carbon nanotube memory cell array program error analysis and tradeoff between reset voltage and verify pulses

Ning

Iwasaki

Hachiya

et al. 2016

Jpn. J. Appl. Phys.

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In emerging non-volatile memories, nano-random access memory (NRAM) has advantages of small program current and high endurance compared with resistive RAM (ReRAM) and phase-change RAM (PRAM). This work comprehensively investigates NRAM set and reset program characteristics by measuring a 116 nm 4 Mbit NRAM cell array. Specifically, reset is found more dependent on reset voltage than reset current. Next, NRAM set and reset bit error rates (BERs) have less significant reduction compared with the increased ratio of set and reset pulse widths. The reset BER can also be reduced by applying multiple reset pulses. Moreover, 108 write cycles are measured on 256 bytes NRAM cells, no wear-out or broken cell is found. Finally, the program characteristics of two verify-reset schemes are compared. The maximum verify-reset voltage can be reduced by increasing the number of reset pulses.

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Investigation and Improvement of Verify-Program in Carbon Nanotube-Based Nonvolatile Memory

Cited by 16 publications

References 17 publications

Review: Electrostatically actuated nanobeam-based nanoelectromechanical switches – materials solutions and operational conditions

Review: Electrostatically actuated nanobeam-based nanoelectromechanical switches – materials solutions and operational conditions

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

Carbon nanotube memory cell array program error analysis and tradeoff between reset voltage and verify pulses

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