Leakage Controlled Read Stable Static Random Access Memories

Abstract

<p class="MsoNormal" style="text-align: left; margin: 0cm 0cm 0pt; layout-grid-mode: char;" align="left"><span class="text"><span style="font-family: ";Arial";,";sans-serif";; font-size: 9pt;">Semiconductor manufacturing process scaling increases leakage and transistor variations, both of which are problematic for static random access memory (SRAM). Since SRAM is a critical component in modern CMOS integrated circuits, novel approaches to addressing these problems are needed. Here, six and seven transistor SRAM cells are presented that do not suffer from reduced stability when read. The cells reside in a low leakage, voltage collapsed, low standby power mode when not being accessed. Both six transistor and seven transistor variations of the basic approach are explored through simulation and measured results. The circuit topology, layout, and impact on memory design of the proposed cell designs are described. Measured results on a 130 nm foundry fabrication process demonstrate the viability of three of the possible cell configurations. Circuit simulation is used to explore the cell stability in the presence of process variations, and to show the value of the proposed SRAM cell designs on future scaled manufacturing technologies.</span></span><span style="font-family: ";Arial";,";sans-serif";; font-size: 9pt;"></span></p&gt

Low-power reliable SRAM cell for write/read operation

“…Since, cache accesses include both read and write operations, therefore, it is required to reduce the power consumption during both operations. Many researchers have paid their attention for reducing the power consumption during write operation [3,4,5] and others for reducing the read power [5,6,7]. The proposed ZA [3] as well as low power 7T [4] SRAM cells are designed for power reduction in write '0' operation.…”