Local Defect Density in Polycrystalline High-k Dielectrics: CAFM-Based Evaluation Methodology and Impact on MOSFET Variability

Methodology for the Simulation of the Variability of MOSFETs With Polycrystalline High-k Dielectrics Using CAFM Input Data

“…With the aim of studying the impact of the polycrystalline dielectric structure on the MOSFET device variability, an annealing process was carried out at 1000 °C, which lead to the polycrystallization of the high-k layer. The presence of the SiO2 layer was taken into account during the TCAD simulations, as reported in [11]. However, SiO2 charges and tox fluctuations in SiO2 were considered to be negligible when compared to those linked to the polycrystalline high-k dielectrics.This is justified by the fact that SiO2 is not polycrystalline and because the amount of charges is expected to be larger in HfO2 than in SiO2.…”

“…However, some high-k materials show a polycrystalline structure [3], [4], which could affect the electrical properties of scaled devices [5] by increasing the leakage current and the deviceto-device variability. Since high-k polycrystallization takes place at the nanometer scale [4], Conductive Atomic Force Microscopy (C-AFM) has been demonstrated to be a very powerful technique to evaluate at the suitable scale the morphological and electrical properties [6]- [10] of polycrystalline high-k dielectrics [11]- [15]. As an example, it has been found that in some polycrystalline Hafnium Dioxide (HfO2) layers, the gate leakage current mainly flows through grain boundaries (GBs) [16], where a reduced oxide thickness (tox) was measured [3].…”

“…Traditionally, due to the lack of experimental data, variability studies are done via the implementation of physical models that mimic the real behavior of the sources of fluctuations [5], [17], [18]. However, more recently a new methodology was proposed in [11]. It consisted in the simulation (using Technology Computer-Aided Design, TCAD [19]) of the I-V curves of MOSFETs whose gate oxide properties were directly determined from experimental data to more accurately link variability sources at the nanoscale with the variability of figures of merit of MOSFETs.…”

“…It consisted in the simulation (using Technology Computer-Aided Design, TCAD [19]) of the I-V curves of MOSFETs whose gate oxide properties were directly determined from experimental data to more accurately link variability sources at the nanoscale with the variability of figures of merit of MOSFETs. In particular, a CAFM was used to measure topographical and current maps of polycrystalline high-k dielectrics (from which nanoscale tox and charge density, ρox maps were obtained [11]) and a simulator was used to evaluate their impact on the MOSFET threshold voltage (Vth). However, in that work, a statistical analysis was not possible.…”

Enhanced Electrical Properties of Atomic Layer Deposited LaxAlyO Thin Films with Stress Relieved Preoxide Pretreatment

“…Among various dielectric materials, La x Al y O is a promising alternative for the post-HfO 2 films due to its high dielectric constant ( k ~25–27), wide band gap (>5 eV), and high band offsets with respect to Si (>2 eV) [7,8]. However, the deposition of high- k gate dielectric films, whether HfO 2 or La x Al y O, on Si substrate, results in poorer interfaces between gate dielectrics and Si than that between thermally grown SiO 2 and Si substrate [9,10]. High-density defects in the bulk of high- k gate dielectrics and in the interfaces of the gate stack structures are the major causes for instability problems as well as mobility degradation [11].…”