Low-Frequency Noise Investigation and Noise Variability Analysis in High- $k$/Metal Gate 32-nm CMOS Transistors

López, Diana; Haendler, S.; Leyris, C.; Bidal, G.; Ghibaudo, G.

doi:10.1109/ted.2011.2141139

Cited by 52 publications

(40 citation statements)

References 23 publications

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“…For the fits in Fig. 2(a) and (b), values of µ eff = 1300 cm 2 /Vs [13] and 3500 cm 2 /Vs [28] were used for the vertical and the planar devices, respectively, C g was typically about half the value of the geometrical oxide capacitance, and α typically varied between 2 × 10 4 and 10 3 Vs/C, which is in agreement with values from literature [11,29,30]. The simplest approach to (ii) is calculating N bt pointwise from the measured S I D and (1) (with α = 0).…”

Section: Results and Analysissupporting

confidence: 81%

“…3(a) and their shapes resemble the findings in literature. For both (i) and (ii), the values for the NW devices are comparable to those of the planar references and they are comparable to planar Si MOSFETs with HfO 2 gate oxides and a SiO 2 interface layer (EOT <2 nm, values adapted from [30] and [31]). In case (ii), the NW devices actually achieve lower values than both of the planar HfO 2 references.…”

Section: Results and Analysissupporting

confidence: 60%

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Low-frequency noise in nanowire and planar III-V MOSFETs

Hellenbrand

Kilpi

Svensson

et al. 2019

Microelectronic Engineering

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Nanowire geometries are leading contenders for future low-power transistor design. In this study, low-frequency noise is measured and evaluated in highly scaled III-V nanowire metal-oxide-semiconductor field-effect transistors (MOS-FETs) and in planar III-V MOSFETs to investigate to what extent the device geometry affects the noise performance. Number fluctuations are identified as the dominant noise mechanism in both architectures. In order to perform a thorough comparison of the two architectures, a discussion of the underlying noise model is included. We find that the noise performance of the MOSFETs in a nanowire architecture is at least comparable to the planar devices. The input-referred voltage noise in the nanowire devices is superior by at least a factor of four.

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Section: Results and Analysissupporting

confidence: 81%

Section: Results and Analysissupporting

confidence: 60%

Low-frequency noise in nanowire and planar III-V MOSFETs

Hellenbrand

Kilpi

Svensson

et al. 2019

Microelectronic Engineering

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show abstract

“…As the variability of the LF noise becomes increasingly important for deepsubmicrometer CMOS technologies [39], [40], it is of high interest to identify and control its sources. Here, it is clear that besides the absolute oxide trap density, also the trap profile can vary from wafer to wafer and even from device to device.…”

Section: Discussionmentioning

confidence: 99%

On the Oxide Trap Density and Profiles of 1-nm EOT Metal-Gate Last CMOS Transistors Assessed by Low-Frequency Noise

Simoen

Veloso

Higuchi³

et al. 2013

IEEE Trans. Electron Devices

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The low-frequency noise behavior of replacement metal gate high-k/metal-gate MOSFETs with an equivalent oxide thickness of the SiO 2 /HfO 2 bilayer in the range ∼1 nm has been investigated. It will be shown that both the average trap density and its profile derived from the frequency exponent γ of the flicker noise spectra are mainly determined by the interfacial layer (IL) oxide processing, with a higher trap density corresponding with a thinner chemical oxide, compared with a ≤1-nm thermal SiO 2 IL. The thickness of the HfO 2 layer and the metal gate fill has only a marginal impact on the noise power spectral density. It will also be shown that for the extraction of the trap density profiles from the 1/f γ noise spectra accurate values for the tunneling effective mass and barrier height are required.Index Terms-Flicker noise, high-k (HK) gate dielectrics, low-frequency (LF) noise, oxide trap density, tunneling.

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“…The performance of TFTs can be improved by using a gate dielectric with higher specific capacitance [3] because higher specific capacitance leads to lower operation voltage. Insulators with high dielectric constant [4]- [7] and ion gels or ionic liquids with large electric-double-layer (EDL) capacitance have been widely investigated [8]- [10]. For example, the operation voltage of ZnO TFTs gated by Y 2 O 3 and Al 2 O 3 was reduced to 4 V [11].…”

Section: Introductionmentioning

confidence: 99%

Low-Voltage Oxide-Based Electric-Double-Layer TFTs Gated by Stacked $\hbox{SiO}_{2}$ Electrolyte/Chitosan Hybrid Dielectrics

Dou

Jiang

Sun

et al. 2012

IEEE Electron Device Lett.

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Low-voltage oxide-based electric-double-layer (EDL) thin-film transistors (TFTs) gated by stacked SiO 2 electrolyte/chitosan proton-conductor hybrid dielectric have been fabricated on glass substrates at room temperature. Such EDL TFTs exhibit a saturation mobility (μ sat ) of 7.8 cm 2 · V −1 · s −1 , a subthreshold swing (S) of 100 mV/decade, a drain current ON/OFF ratio (I on/off ) of 7.8 × 10 5 , and a threshold voltage (V th ) of −0.48 V. After aging for one month in air ambient without surface passivation, such device shows μ sat of 3.5 cm 2 · V −1 · s −1 , I on/off of 1.2 × 10 5 , and S of 120 mV/decade. Control experiments demonstrate that devices gated by stacked SiO 2 electrolyte/chitosan hybrid dielectrics show improved stability compared with TFTs gated by single chitosan or single SiO 2 electrolyte gate dielectric.

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Low-Frequency Noise Investigation and Noise Variability Analysis in High- $k$/Metal Gate 32-nm CMOS Transistors

Cited by 52 publications

References 23 publications

Low-frequency noise in nanowire and planar III-V MOSFETs

Low-frequency noise in nanowire and planar III-V MOSFETs

On the Oxide Trap Density and Profiles of 1-nm EOT Metal-Gate Last CMOS Transistors Assessed by Low-Frequency Noise

Low-Voltage Oxide-Based Electric-Double-Layer TFTs Gated by Stacked $\hbox{SiO}_{2}$ Electrolyte/Chitosan Hybrid Dielectrics

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