Low-power/low-swing domino CMOS logic

Rjoub, Abdoul; Koufopavlou, O.; Nikolaidis, S.

doi:10.1109/iscas.1998.706792

Cited by 18 publications

(10 citation statements)

References 11 publications

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“…Low-swing dc-dc converter exhibits reduced (27.9 %) power dissipation as compared to a standard full-swing dc-dc converter (Kursun et al 2004;Audzevich et al 2014). Also, various techniques to reduce power consumption in domino logic circuits by lowering the voltage swing are presented in (Liu and Kursun 2006;Rjoub et al 1998;Friedman 2002, 2005).…”

Section: Introductionmentioning

confidence: 99%

Current-mode circuit-level technique to design variation-aware nanoscale summing circuit for ultra-low power applications

et al. 2016

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Section: Introductionmentioning

confidence: 99%

Current-mode circuit-level technique to design variation-aware nanoscale summing circuit for ultra-low power applications

et al. 2016

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“…Moreover, a low-power differential current switch logic family has been introduced in [23]. Finally, low-power Domino logic designs, based on low-voltage swing techniques, have been presented in [24] and [25].…”

Section: Introductionmentioning

confidence: 99%

A Design Technique for Energy Reduction in NORA CMOS Logic

Limniotis

Tsiatouhas

Haniotakis

et al. 2006

IEEE Trans. Circuits Syst. I

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In this work, a design technique to reduce the energy consumption in NO RAce (NORA) circuits is presented. The technique is based on a unidirectional switch topology combined with a new clocking scheme permitting both charge recycling between circuit nodes and elimination of the short circuit current. Calculations proved that energy savings higher than 20% can be achieved. Simulation results from NORA designs in a 0.18-m CMOS technology are presented to demonstrate the effectiveness of the proposed technique to achieve both energy and energy-delay product reduction.Index Terms-Charge recycling, low-power design, NO RAce (NORA) CMOS circuits.

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“…A low swing domino logic circuit without a keeper is compared to a standard full swing domino logic circuit without a keeper in terms of power and delay in [8]. However, noise issues have not been addressed.…”

Section: Introductionmentioning

confidence: 99%

“…However, noise issues have not been addressed. The circuit proposed in [8] is not effective in increasingly noisy high performance integrated circuits. A low swing domino logic circuit is proposed in this paper to reduce the power consumption without degrading the noise immunity.…”

Section: Introductionmentioning

confidence: 99%

Low swing dual threshold voltage domino logic

Kursun

Friedman

2002

Proceedings of the 12th ACM Great Lakes Symposium on VLSI

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A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active power consumption is reduced by up to 9.4% while improving the noise immunity by 2.6% as compared to standard domino logic circuits. It is also shown that by applying a low swing contention reduction technique, the power savings can be further increased by 6.7% while the delay can be improved by 8.6%. A simple and efficient dual threshold voltage (dual-V t ) circuit technique that incorporates low swing signals is also proposed. It is shown that the proposed dual-V t technique reduces the standby leakage current by approximately 235 times while offering enhanced delay characteristics as compared to a standard low threshold voltage implementation.

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Low-power/low-swing domino CMOS logic

Cited by 18 publications

References 11 publications

Current-mode circuit-level technique to design variation-aware nanoscale summing circuit for ultra-low power applications

Current-mode circuit-level technique to design variation-aware nanoscale summing circuit for ultra-low power applications

A Design Technique for Energy Reduction in NORA CMOS Logic

Low swing dual threshold voltage domino logic

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