Low Temperature Atomically Flattening of Si Surface of Shallow Trench Isolation Pattern

Abstract

Low temperature (800 ºC - 900 ºC) Ar annealing for atomically flattening was applied to shallow trench isolation (STI)-patterned wafers where Si and SiO2 coexist on the wafer surface. During the Ar annealing, concentrations of H2O and O2 residual gases in the annealing ambience was maintained at low level less than 30 ppb. Such low temperature and clean Ar ambience can suppress oxidation and etching of Si surface as well as a decomposition of thick SiO2 film for device isolation. As a result, the atomically flat Si surface was obtained for the Si active pattern having STI edge by the Ar annealing at 800 ºC - 900 ºC. Owing to the introduction of the atomically flat Si/gate oxide interface, breakdown characteristic of the fabricated MOS capacitors was improved for the atomically flat devices.

Introduction of Atomically Flattening of Si Surface to Large-Scale Integration Process Employing Shallow Trench Isolation

“…Earlier work has shown that such an atomically flat surface could be obtained for a smaller active region where the MOSFETs with a practical device size were fabricated. 12,30 Figures 3a-3c shows the transmission electron microscopy images of the STI edge in the active area of the nMOSFETs with the gate length (L) and gate width (W) of 0.22 μm and 0.28 μm, respectively, taken for (a) the conventional sample, (b) the sample A and (c) the sample B. The STI edges of sample B (Fig.…”

Evaluation of Low-Frequency Noise in MOSFETs Used as a Key Component in Semiconductor Memory Devices

“…The size of MOSFETs has been downscaled to less than l0 nm and the structure has changed the planer to FinFET, recently. We have to continue the evaluation of To implement the surface flattening process, a low temperature of less than 900 • C and low oxidation species, such as O 2 and H 2 O, must be required [81,82,85]. There is another method for flattening the surface first and keeping it during the process steps preceding gate oxidation [85,87,88].…”

“…The interface roughness degrades not only electron mobility [66][67][68][69][70][71] and gate dielectric reliability [72][73][74], but also noise generation [71,75,76]. An atomically flat interface [77][78][79][80][81][82][83][84] is effective for reducing low-frequency noise [79,[83][84][85][86][87].…”

“…The average roughness in the trace of the atomically flat interface was less than 0.04 nm, which is the detection limit of our AFM system. L = 0.135 tan θ (nm) (16) To implement the surface flattening process, a low temperature of less than 900 °C and low oxidation species, such as O2 and H2O, must be required [81,82,85]. There is another method for flattening the surface first and keeping it during the process steps preceding gate oxidation [85,87,88].…”

Random telegraph noise measurement and analysis based on arrayed test circuit toward high S/N CMOS image sensors

“…With these result, the channel percolation due to the potential variation by interface roughness should be suppressed by an introduction of atomically flat interface. The atomically flattening technology has been introduced for 0.22 !lm CMOS process with shallow trench isolation [23,[41][42]. Fig.…”