Low voltage and low power embedded 2T-SONOS flash memories improved by using P-type devices and high-K materials

Wet oxidation of nitride layer implanted with low-energy Si ions for improved oxide-nitride-oxide memory stacks

“…Due to its promising in terms of scalability, the conventional polycrystalline silicon/oxide/ nitride/oxide/silicon memory cell has regained a lot of attention nowadays. 2,3 Typical fabrication of the oxide/nitride/oxide ͑ONO͒ stack consists in the growth of a thin SiO 2 layer on a Si substrate and subsequent deposition of a Si 3 N 4 layer. The top silicon oxide is obtained by either deposition techniques or high temperature wet oxidation 4,5 of the Si 3 N 4 layer.…”

Programme and retention characteristics of SONOS memory arrays with layered tunnel barrier

“…Note that the memory devices presented in this paper are meant to be used in twotransistor (2T) NOR and E 2 PROM configurations, where a select gate in each cell ensures immunity to over-erase. In such a 2T-configuration negative erased V T such as those shown in figure 5 are even an advantage as they enable low-voltage read [5]. Threshold voltages in the programmed state are given by the curves with filled symbols, whereas the curves with open symbols display the threshold voltages in the erased state.…”

“…In addition, SONOS memories are particularly attractive for embedded applications, as they considerably facilitate integration, simplifying it to a single-poly process. However, SONOS memories aimed at low power and low voltage applications, programmed/erased by direct tunnelling of charge from the silicon (Si) channel with moderately low programme/erase (P/E) voltages V P /E ∼ = ±10 V, suffer from inherent retention problems [3][4][5]. Efficient programming and, in particular, erasing by tunnelling are only possible if the bottom silicon dioxide SiO 2 is sufficiently thin, typically around 2-2.5 nm.…”

“…The remaining V T window, defined as the difference between the programmed and erased threshold voltages, after 10 years is typically very low and makes the reliable readout of SONOS devices very difficult. Thicker tunnel oxides ensure a good charge retention over 10 years, but the operation of such SONOS devices by tunnelling, especially with n + -doped poly-Si gates, may result in a limited V T -window, due to the well-known phenomenon of erase saturation [5,6]. Si N 3 4 Si N 3 4 Si N Besides, unlike thin-oxide SONOS devices, whose endurance is virtually independent of cycling up to as many as 10 7 P/E cycles, thick-oxide SONOS devices have a limited endurance and, thus, a limited range of applications [6,7].…”

“…The remaining V T window, defined as the difference between the programmed and erased threshold voltages, after 10 years is typically very low and makes the reliable readout of SONOS devices very difficult. Thicker tunnel oxides ensure a good charge retention over 10 years, but the operation of such SONOS devices by tunnelling, especially with n + -doped poly-Si gates, may result in a limited V T -window, due to the well-known phenomenon of erase saturation [5,6].…”