Low voltage operation of GaN vertical nanowire MOSFET

Son, Dae‐Ho; Jo, Young-Woo; Seo, Jae Hwa; Won, Chul-Ho; Im, Ki‐Sik; Lee, Yong Soo; Jang, Hwan Soo; Kim, Dae-Hyun; Kang, In Man; Lee, Jung‐Hee

doi:10.1016/j.sse.2018.03.001

Cited by 32 publications

(26 citation statements)

References 23 publications

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“…Fig. 5 (a) shows the field-effect mobility versus gate overdrive voltage (V G -V TH ) for the investigated GaN VNW-MOSFETs [15], exhibiting the mobility decrease as d NW narrows. When V G is less than V FB , the channel current consists of electron flow through the nanowire volume where the mobility is superior.…”

Section: Resultsmentioning

confidence: 99%

“…Indeed, relatively small permittivity and large electron effective mass of the GaN-based materials are important parameters for alleviating the short channel effects because they reduce the source-to-drain tunneling current and the natural length which represents the penetration distance of the electric field lines from the drain [10]. Recently, GaNbased 3-dimsional FETs with gate-all-around (GAA) structures have shown improved device performances such as linearity, suppressed current collapse, high on/off-state current ratio, and high voltage characteristics, resulting from the enhanced gate control of the channel [11][12][13][14][15]. Especially, GaN vertical nanowire MOSFET features small threshold voltage of ~ 0.6 V and saturation drain voltage of less than 1 V which open up possibility of GaN devices as a future logic applications [15].…”

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confidence: 99%

“…The device with d NW of 120 nm has hexagonal nanowire pillar with m-plane sidewall surface and the devices with d NW of 75 and 45 nm have non-hexagonal nanowire pillar with various crystalline planes in the sidewall. The GaN VNW-MOSFET with d NW of 120 nm exhibits considerably lower saturation drain voltage (< 0.5 V) compared to conventional GaN-based planar devices because the drain current in such a narrow nanowire channel can be easily pinched-off due to the electric field distribution between the gate and the drain[15].On the other hand, the output characteristics of the device with d NW of 75 nm show even lower saturation voltage at low current level, but exhibit a kink (second rise in drain current) at drain voltage (V D ) of 0.5 ~ 0.6 V. Furthermore, the device with d NW of 45 nm shows output characteristics with offsetlike turn-on voltage at V D = ~ 0.5 V. For V D < 0.5 V, the drain current is two orders of magnitude lower than in the device with d NW of 75 nm. These contrasting behaviors can be understood from the simulations of the electric field distribution.…”

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confidence: 99%

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Effects of Contact Potential and Sidewall Surface Plane on the Performance of GaN Vertical Nanowire MOSFETs for Low-Voltage Operation

Son

Thingujam

Kim

et al. 2020

IEEE Trans. Electron Devices

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HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L'archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de  Abstract--GaN-based materials are expected to show excellent immunity against short-channel effects because they have relatively lower permittivity and higher electron effective mass, compared to other materials such as Si, Ge, and In(Ga)As. To further reduce the short-channel effects, it is important to enhance the gate controllability of the device by utilizing a gateall-around structure. In this work, GaN vertical GAA nanowire MOSFETs with various diameters of 120, 75, and 45 nm have been fabricated. The device with a diameter of 120 nm shows threshold voltage of 0.7 V, drain saturation voltage of 0.5 V, and subthreshold swing of 70 mV/decade, which would be suitable for low voltage/power applications. However, the devices with smaller diameter of 75 and 45 nm show peculiar characteristics, such as a second rise of the drain current in output characteristics and a negative transconductance. Systematical analyses with dc and noise measurements as well as TCAD simulations show that the observed characteristics are due to the contact potential which strongly depends on the nanowire diameter and the trapping effect into deep traps at the sidewall surface of the nanowire channel. Index Terms--GaN vertical nanowire MOSFET, low voltage application, nanowire diameter, contact potential, negative transconductance I. INTRODUCTION -V semiconductors such as GaAs and InAs offer superior material and electrical properties and are considered to replace the channel layers in the conventional Si-based devices which technologies have been quiet close to their limitations [1-6]. In contrast with other III-V

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Section: Resultsmentioning

confidence: 99%

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confidence: 99%

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confidence: 99%

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Effects of Contact Potential and Sidewall Surface Plane on the Performance of GaN Vertical Nanowire MOSFETs for Low-Voltage Operation

Son

Thingujam

Kim

et al. 2020

IEEE Trans. Electron Devices

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“…In general, GaN-based nanowire FETs are thus attractive for high-end applications such as high-power, high-speed, and high-temperature due to high surface to volume ratio [13,14]. It has been reported in the literature that Al2O3 as a gate oxide is best suited for GaNNW MOSFET owing to no hysteresis (i.e., forward and backward sweep Vth shift of ~0.2V) in comparison to conventional SiO2 which shows large hysteresis [8,15]. Also, in terms of fabrication GaNNW/Al2O3 MOSFETs were believed to provide more stable process than SiNW/SiO2 FETs in terms of interface traps [16,17].…”

Section: Introductionmentioning

confidence: 99%

Suppressed Distortion Performance Metrics of 20nm GAA-GaN/Al2O3 Nanowire MOSFET: Based on Quantum Numerical Simulation 

Gupta¹,

Jain

Kumar

2021

Preprint

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This work investigates the suppressed distortion performance metrics of gate all around (GAA) Gallium Nitride (GaN)/Al2O3 Nanowire (NW) n-channel MOSFET (GaNNW/Al2O3 MOSFET) based on quantum numerical simulations at room temperature (300 K). The simulation results show high switching ratio (≈109) with low subthreshold swing (67mV/decade), high QF value (4.1mS-decade/mV) of GaNNW/Al2O3-MOSFET in comparison to GaNNW/SiO2 and SiNW MOSFET for Vds=0.4V due to the lower permittivity of GaN and more effective mass of the electron. Furthermore, linearity and distortion performance is also examined by numerically calculating transconductance and its higher derivatives (gm2 and gm3); voltage and current intercept point (VIP2, VIP3 and IIP3); 1-dB compression point; Harmonics distortions (HD2 and HD3) and IMD3. All these parameters show high linearity and low distortion at zero crossover point (where gm3=0) in GaNNW/Al2O3 MOSFET. Thus, GaNNW MOSFET can be considered as a promising candidate for low power high-performance applications. In addition, effect of ambient temperature (250K-450K) on the performance of GaNNW/Al2O3 is studied and discussed in terms of the above mentioned metrics. It is very well exhibited that SS, Ion, Vth, and QF improved when the temperature is lowered which makes it suitable for low-temperature environments. But, linearity degrades as the temperature lowers down.

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“…other groups [13], [14]. They ensure E-mode operation and potentially scale down the device size compared to the lateral architecture.…”

Section: Introductionmentioning

confidence: 99%

Demonstration of UV-Induced Threshold Voltage Instabilities in Vertical GaN Nanowire Array-Based Transistors

Ruzzarin

Meneghini

Santi

et al. 2019

IEEE Trans. Electron Devices

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This paper investigates the degradation of vertically aligned gallium nitride (GaN) nanowire (NW) arrays submitted to gate bias stress and UV light. Based on electrical tests and simulations, we demonstrate the existence of trapping processes that depend on the applied stress voltage V Gstress and on the applied light during stress (wavelength, λ). We demonstrate the following original results: 1) for positive and negative V Gstress conditions, no significant variation in dc characteristics is observed when the samples are stressed in dark and 2) when the devices are submitted to negative V Gstress and to UV light, a positive variation in threshold voltage (V th) is observed. The positive V th shift is ascribed to the transfer and trapping of electrons from the gate metal to the oxide, promoted by UV light. We also evaluated the temperature dependence of the threshold voltage shift under UV light. We demonstrated an increased trapping at higher temperatures, indicating a role of thermionic processes in electron trapping. On the other hand, detrapping from oxide states proceeds through defect-mediated conduction, i.e., is limited by the number of available states.

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Low voltage operation of GaN vertical nanowire MOSFET

Cited by 32 publications

References 23 publications

Effects of Contact Potential and Sidewall Surface Plane on the Performance of GaN Vertical Nanowire MOSFETs for Low-Voltage Operation

Effects of Contact Potential and Sidewall Surface Plane on the Performance of GaN Vertical Nanowire MOSFETs for Low-Voltage Operation

Suppressed Distortion Performance Metrics of 20nm GAA-GaN/Al2O3 Nanowire MOSFET: Based on Quantum Numerical Simulation

Demonstration of UV-Induced Threshold Voltage Instabilities in Vertical GaN Nanowire Array-Based Transistors

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Low voltage operation of GaN vertical nanowire MOSFET

Cited by 32 publications

References 23 publications

Effects of Contact Potential and Sidewall Surface Plane on the Performance of GaN Vertical Nanowire MOSFETs for Low-Voltage Operation

Effects of Contact Potential and Sidewall Surface Plane on the Performance of GaN Vertical Nanowire MOSFETs for Low-Voltage Operation

Suppressed Distortion Performance Metrics of 20nm GAA-GaN/Al2O3 Nanowire MOSFET: Based on Quantum Numerical Simulation&nbsp;

Demonstration of UV-Induced Threshold Voltage Instabilities in Vertical GaN Nanowire Array-Based Transistors

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Suppressed Distortion Performance Metrics of 20nm GAA-GaN/Al2O3 Nanowire MOSFET: Based on Quantum Numerical Simulation