Mismatch characterization of small size MOS transistors

Bastos, J.; Steyaert, Michiel; Roovers, R.; Kinget, Peter R.; Sansen, Willy; Graindourze, B.; Pergoot, A.; Janssens, Edmond

doi:10.1109/icmts.1995.513986

Cited by 74 publications

(28 citation statements)

References 5 publications

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“…The random mismatch of two closely spaced, identical MOS transistors can be measured in terms of the variation in the drain current which is shown in (1) and has been extensively investigated down to deep-submicron device sizes [5] [12]- [14].…”

Section: A Random Mismatch Modelmentioning

confidence: 99%

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Symmetry constraint based on mismatch analysis for analog layout in SOI technology

Liu¹,

Dong²,

Hong³

et al. 2008

2008 Asia and South Pacific Design Automation Conference

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-The conventional tools for mismatch elimination such as geometric symmetry and common centroid technology can only eliminate systematic mismatch, but can do little to reduce random mismatch and thermal-induced mismatch. As the development of VLSI technology, the random mismatch is becoming more and more serious. And in the context of Silicon on Insulator (SOI), the self-heating effect leads to unbearable thermal-induced mismatch. Therefore, in this paper, we first propose a new model which can estimate the combination effect of both random mismatch and thermal-induced mismatch by mismatch analysis and SPICE simulation. And in order to meet the different sensitivities of different symmetry pairs, an automatic classification tool and a configurable optimization process are also introduced. All of these are embedded in the floorplanning process. The final experimental results prove the effectiveness of our method.

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Section: A Random Mismatch Modelmentioning

confidence: 99%

“…Device-to-device variations which are defined as the random mismatch are caused by some unpredictable processes during design and fabrication phases. And random mismatch will greatly increase as the size of transistors decreases [12]- [14]. Nowadays, the size of transistor is in the magnitude of deep-submicron.…”

Section: Introductionmentioning

confidence: 99%

Symmetry constraint based on mismatch analysis for analog layout in SOI technology

Liu¹,

Dong²,

Hong³

et al. 2008

2008 Asia and South Pacific Design Automation Conference

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“…In nanometer technologies, extra modeling terms are used to accurately model the threshold voltage variation of narrow-channel transistors and short-channel transistors [5], [41]. In this context, Tuinhout introduced a benchmark of 1mV · µm/nm of gate oxide to forecast the matching performance of scaling CMOS technologies [43].…”

Section: Variability As a Yield Influencing Effectmentioning

confidence: 99%

“…A normal distribution with mean equal to zero and variance dependent on the width W , the length L and the mutual distance D of the transistors is a widely accepted model for these random variations [5], [31]:…”

Section: Variability As a Yield Influencing Effectmentioning

confidence: 99%

Emerging yield and reliability challenges in nanometer CMOS technologies

Gielen

Wit

Maricau

et al. 2008

Proceedings of the Conference on Design, Automation and Test in Europe

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With further scaling of nanometer CMOS technologies, yield and reliability become an increasing challenge. This paper reviews the most important phenomena affecting yield and reliability. For each effect, the basic physical mechanisms causing the effect and its impact on transistor parameters are described. Possible solutions to cope/handle with these effects on the design level are discussed as well.

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“…For nanometer technologies (e.g., below 90nm) this is reflected in a stochastic component of variability that becomes much more prominent than any other systematic effects [1]. Due to the extremely small dimensions of the transistors in nanometer technologies, the same variation in the number of dopant atoms have a much higher impact in the electrical properties of the device than in earlier technology nodes.…”

Section: Introductionmentioning

confidence: 99%