Mixed CNT bundles as VLSI interconnects for nanoscale technology nodes

Dhillon, G. S.; Sandha, Karmjit Singh

doi:10.1007/s10825-020-01585-4

Cited by 9 publications

(4 citation statements)

References 36 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Theoretically, the transport speed of CNT for long-distance transport is much better than that of Cu. It is worth mentioning that some studies have shown the mixed-CNT bundle has better performance than using SWCNT bundles [ 48 , 77 ]. However, it is limited by complex distribution requirements and process challenges; its practical application still needs further investigation.…”

Section: On-chip Interconnectmentioning

confidence: 99%

“…Rhombus patterns represent the related reference [ 32 ]. For global level, square patterns represent the related references [ 20 , 21 , 22 , 23 , 24 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 , 46 , 47 , 48 ], from left to right respectively. Rhombus patterns represent the related references [ 23 , 24 , 45 , 49 ], from left to right respectively.…”

Section: Figurementioning

confidence: 99%

See 1 more Smart Citation

Recent Progress and Challenges Regarding Carbon Nanotube On-Chip Interconnects

Chen

Zhou

et al. 2022

Micromachines

View full text Add to dashboard Cite

Along with deep scaling transistors and complex electronics information exchange networks, very-large-scale-integrated (VLSI) circuits require high performance and ultra-low power consumption. In order to meet the demand of data-abundant workloads and their energy efficiency, improving only the transistor performance would not be sufficient. Super high-speed microprocessors are useless if the capacity of the data lines is not increased accordingly. Meanwhile, traditional on-chip copper interconnects reach their physical limitation of resistivity and reliability and may no longer be able to keep pace with a processor’s data throughput. As one of the potential alternatives, carbon nanotubes (CNTs) have attracted important attention to become the future emerging on-chip interconnects with possible explorations of new development directions. In this paper, we focus on the electrical, thermal, and process compatibility issues of current on-chip interconnects. We review the advantages, recent developments, and dilemmas of CNT-based interconnects from the perspective of different interconnect lengths and through-silicon-via (TSV) applications.

show abstract

Section: On-chip Interconnectmentioning

confidence: 99%

Section: Figurementioning

confidence: 99%

Recent Progress and Challenges Regarding Carbon Nanotube On-Chip Interconnects

Chen

Zhou

et al. 2022

Micromachines

View full text Add to dashboard Cite

show abstract

“…16 Singh et al 1,5,6 proposed an equivalent circuit model for SWCNT bundle, which shows the various electron-phonon scattering mechanisms dependency as the function of the temperature. For copper, SWCNT, MWCNT, DWCNT, and mixed CNT bundle structures, many works analyzed the performance in terms of propagation delay, power dissipation and power delay product at nanoscaled technology nodes, [17][18][19] and an analysis of the delay under process-induced variations were also performed. 20 These works focused on the propagation delay of CNT instead of the crosstalk effect between interconnects.…”

Section: Introductionsmentioning

confidence: 99%

Effect of temperature and single event transient on crosstalk in coupled single‐walled carbon nanotube (SWCNT) bundle interconnects

Liu

Li²,

et al. 2021

Circuit Theory & Apps

View full text Add to dashboard Cite

Although they have better electrical and thermal properties, thermal issues have become an important challenge to design modern integrated circuits with single-walled carbon nanotube (SWCNT) bundle interconnects. The equivalent RLC model for SWCNT bundle interconnect is analyzed. Based on the proposed circuit for single event crosstalk (SEC), the influences of the length of line, nanotube diameter, metallic nanotube ratio, and technology node on SEC at different temperatures are studied. The potential impact mechanisms are also discussed. The simulation results show that, compared with one in copper line, peak voltage and pulse width of SEC in SWCNT interconnect are reduced by an average of 23.7% and 8.8%, respectively. The larger the diameter of SWCNT is or the more the ratio of metallic SWCNT is, the weaker the effect of SEC will be. With the increase of the length of line, the crosstalk effect will increase. The pulse width of SEC is more sensitive to the temperature when the length of line is longer. However, the peak voltage is more sensitive to the temperature when the length of line is shorter. As the technology node shrinks from 21 nm to 9.5 nm, the noise area of SEC increases from 0.55 V•ns to 1.89 V•ns, which results in that the crosstalk action time increases significantly.

show abstract

“…While further scaling down the feature size, the researchers are confronting major challenges not only from the CMOS design but also due to interconnects, some of which are directly imposed due to quantum effects [11]. To solve this problem, several other technologies are being explored such as nanowires, nanotubes [12], [13], [14], [15], [16], [17], Quantum wires [18], [19], [17], [20], etc. other than metallic interconnects [21].…”

Section: Introductionmentioning

confidence: 99%

Machine Learning Techniques for Modeling and Performance Analysis of Interconnects

Tripathi¹,

Vaghasiya²,

Junjariya³

et al. 2021

IEEE Open J. Nanotechnol.

View full text Add to dashboard Cite

Interconnects are essential components of any electronic system. Their design, modeling and optimization are becoming complex and computationally expensive with the evolution of semiconductor technology as the devices of nanometer dimensions are being used. In high-speed applications, system level simulations are needed to ensure the robustness of a system in terms of signal and power quality. The simulations are becoming very expensive because of the large dimensional systems and their full-wave models. Machine learning techniques can be used as computationally efficient alternatives in the design cycle of the interconnects. This paper presents a review of the applications of machine learning techniques for design, optimization and analysis of interconnects in high-speed electronic systems. A holistic discussion is presented, including the basics of interconnects, their impact on the system performance, popular machine learning techniques and their applications related to the interconnects. The performance evaluation, optimization and variability analysis of interconnects are discussed in detail. Future scope and overlook that are presented in the literature are also discussed.

show abstract

Mixed CNT bundles as VLSI interconnects for nanoscale technology nodes

Cited by 9 publications

References 36 publications

Recent Progress and Challenges Regarding Carbon Nanotube On-Chip Interconnects

Recent Progress and Challenges Regarding Carbon Nanotube On-Chip Interconnects

Effect of temperature and single event transient on crosstalk in coupled single‐walled carbon nanotube (SWCNT) bundle interconnects

Machine Learning Techniques for Modeling and Performance Analysis of Interconnects

Contact Info

Product

Resources

About