Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies

Torres, Cynthia A.; Miller, James W.; Stockinger, Michael; Akers, Matthew D.; Khazhinsky, M.G.; Weldon, J.C.

doi:10.1016/s0026-2714(02)00051-3

Cited by 25 publications

(8 citation statements)

References 3 publications

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“…For instance, a large number of time constant values ranging from 100ns [Ker 1999] to 2μs [Poon and Maloney 2003] have been quoted in the literature for these rail clamp circuits. Other values quoted include greater than 1,000ns [Torres et al 2001;Li et al 2006], 866ns [Stockinger et al 2003] and 1.5μs to 2s [Maloney and Kan 1999]. Further, from discussions with designers, we have learned that some designers are only comfortable with higher-value time constants, up to 5μs.…”

Section: Prior Workmentioning

confidence: 95%

Process Independent Design Methodology for the Active RC and Single-Inverter-Based Rail Clamp

Venkatasubramanian

Elio

Ozev

2016

ACM Trans. Des. Autom. Electron. Syst.

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RC and single-inverter-based rail clamps are widely used in semiconductor products for electrostatic discharge (ESD) protection. We propose a technology-node-independent design methodology for these rail clamp circuits that takes process, voltage, and temperature variations into consideration. The methodology can be used as a cookbook by the designer or be used to automate the entire design process. Tradeoffs between various design metrics such as ESD performance (Human Body Model), leakage, and area are considered. Simplified circuit models for the rail clamp are presented to gain insights into its working and to size the circuit components. A rail clamp for core power domain is designed using the proposed approach in 40nm low-power process and performance results of the design are also presented. The effectiveness of the design methodology is proven in three different technology nodes by comparing the obtained design with the best design from among 250,000 designs obtained by randomly sampling from the design space. ACM Reference Format:Ramachandran Venkatasubramanian, Robert Elio, and Sule Ozev. 2016. Process independent design methodology for the active RC and single-inverter-based rail clamp.

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Section: Prior Workmentioning

confidence: 95%

Process Independent Design Methodology for the Active RC and Single-Inverter-Based Rail Clamp

Venkatasubramanian

Elio

Ozev

2016

ACM Trans. Des. Autom. Electron. Syst.

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“…Finally, it should be emphasized that unlike NMOSbased clamping device [12] where the CR signal should detect an ESD event and drive the cell as long as the ESD event is present, once triggered the STMSCR will remain on by its own latching mechanism. The RC signal is therefore no more needed to control the operation of the protection.…”

Section: Cr Cell Designmentioning

confidence: 99%

A new multi-finger SCR-based structure for efficient on-chip ESD protection

Azaïs

Caillard

Dournelle

et al. 2005

Microelectronics Reliability

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“…A second ESD design practice focus area is the placement and synthesis of the RC-triggered MOSFET power clamps into a semiconductor chip [33][34][35][36]. It has been well known that as the distribution of ESD power clamps are placed with an increased frequency, the ESD input distribution improves in terms of the mean and the width of the distribution; not only does the total ESD pin Gaussian mean increase, but also the ESD pin Gaussian standard deviation.…”

Section: Rc-triggered Mosfet Esd Power Clamps Placementmentioning

confidence: 99%

“…By mid 1990s, diode string [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17], 3,[20][21][22][23][24][25][26][27], and bipolar ESD power clamps [43][44][45][46][47][48][49], and silicon-controlled rectifiers [50-60] became part of the ESD design methodology and practice. From 1995 to 2005, the focus on the MOSFET ESD power clamps have been on producing a better ESD power clamp, design integration, physical placement [33][34][35][36], and low leakage [38]. In the other technologies, the focus has been extending the concepts to triple-well CMOS [11,12], BiCMOS, silicon germanium [10,[13][14][15][45][46][47], gallium arsenide [48,49], and silicon-oninsulator (SOI) technologies …”

mentioning

confidence: 99%

ESD Power Clamps

2005

Esd

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An electrostatic discharge (ESD) design practice is the integration of ESD power clamps between the power supply rails. ESD power clamps popularity occurred in the 1990s to achieve better ESD results in semiconductor chips [1][2][3][4][5][6]. By mid 1990s, diode string [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17], 3,[20][21][22][23][24][25][26][27], and bipolar ESD power clamps [43][44][45][46][47][48][49], and silicon-controlled rectifiers [50-60] became part of the ESD design methodology and practice. From 1995 to 2005, the focus on the MOSFET ESD power clamps have been on producing a better ESD power clamp, design integration, physical placement [33][34][35][36], and low leakage [38]. In the other technologies, the focus has been extending the concepts to triple-well CMOS [11,12], BiCMOS, silicon germanium [10,[13][14][15][45][46][47], gallium arsenide [48,49], and silicon-oninsulator (SOI) technologies [17][18][19]. ESD power clamps achieve both functional and ESD advantages. ESD power clamps achieve ESD robustness and electrical overstress (EOS) robustness by enhancing the ESD design practice as follows:Establishment of ESD Current Loops: The addition of power clamps provides an alternative current loop for the ESD current.Bidirectional Current Paths: Bidirectional current flow allows the flow of the ESD current through the loop in both directions.Segmented Chip Current Path: ESD power clamps can be placed between independent and disconnected chip segments allowing electrical connectivity.Rail-to-Rail ESD Protection: Rail-to-rail ESD protection between the two power rails is achieved using the power clamp placed between the two power rails.Pin-to-Pin ESD Protection: Pin-to-Pin ESD protection is achieved by establishing bidirectional current paths from the first pin, through the power clamp and to the second pin. ESD: Circuits and Devices Steven H. Voldman

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Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies

Cited by 25 publications

References 3 publications

Process Independent Design Methodology for the Active RC and Single-Inverter-Based Rail Clamp

Process Independent Design Methodology for the Active RC and Single-Inverter-Based Rail Clamp

A new multi-finger SCR-based structure for efficient on-chip ESD protection

ESD Power Clamps

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