Motivations towards BIST and DfT for embedded charge-pump phase-locked loop frequency synthesisers

Burbidge, M.; Lechner, A.; Bell, G.; Richardson, A.

doi:10.1049/ip-cds:20040619

Cited by 10 publications

(3 citation statements)

References 11 publications

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“…The independence of the two schemes reduces resource sharing. The paper [10] takes production test and characterization as well as their common parts into account, but it can't be analyzed the relationship between parameters in detail, and the solution costs long test time.…”

Section: Proposed Pll Bist Schemementioning

confidence: 99%

A Hybrid Low-Cost PLL Test Scheme based on BIST Methodology

Cai¹,

Que²,

Liu³

et al. 2015

Advances in Intelligent Systems Research

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In this paper, a hybrid built-in self-test (BIST) scheme is firstly proposed for phase-locked loop (PLL) production test and performance characterization. The scheme combines the structure test and function test in production test operation. The former is to detect hard faults and the latter is used to improve the soft fault coverage. Jitter measurement is selected as a typical parameter test in performance characterization mode, which includes vernier delay line (VDL) to measure timing jitter and undersampling technology to measure cycle-cycle jitter. The goal of the scheme is to enable complete production quality test and exact performance characterization.

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Section: Proposed Pll Bist Schemementioning

confidence: 99%

A Hybrid Low-Cost PLL Test Scheme based on BIST Methodology

Cai¹,

Que²,

Liu³

et al. 2015

Advances in Intelligent Systems Research

View full text Add to dashboard Cite

show abstract

“…The proposal in [8] digitally programs the CP and observes the loop filter output -we refrain from sampling the VCO input node as any excessive capacitance added at that node may affect the settling time characteristics. Some of approaches involve addition duplicate modules or using ATE to provide some of the internal node voltages [9] -this approach does not complete enable self-test as the stimuli are provided externally. i.e.-if the LF output/VCO input is provided externally using the Per Pin Measurement Unit (PPMU) of ATE, the CP/loop filter blocks remain untested and an additional mechanism would be required to these these parts.…”

Section: Introductionmentioning

confidence: 99%

Closed-loop Built in Self Test for PLL production testing with minimal tester resources

Dasnurkar

Abraham

2009

2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop

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Phase Locked Loops (PLLs) are extensively used in modern System on a Chip (SoC) modules for generating timing, clock signal recovery and to provide a timing reference for communication interfaces. Due to their use in crucial and omnipresent applications, PLLs are the only mixed signal components on many otherwise digital blocks. The mixed signal nature makes testing of PLLs complicated as the output test requirements include non-digital parameters such as phase error, lock time, jitter along with the typical frequency locking test. Automatic Test Equipment (ATE) resources needed for these added parameters may require the use of a higher-end ATE for an otherwise digital block, driving up the production test costs. Built in Self Test (BiST) approaches for PLLs need to be carefully designed due to the load-sensitive nature of the internal analog nodes as well as sensitivity of the feedback path to any added delays by the BiST overhead. Our scheme proposes a mixedsignal closed loop complete test solution for a PLL by injecting a BiST signal at non-sensitive internal nodes and observing a low frequency(LF)/DC output in order to perform a pass/fail decision on the PLL. The goal of this scheme is to enable complete production quality at-speed testing of a PLL using minimal ATE resources.

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“…Various BIST techniques have been proposed such as charge-based frequency measurement and ramp-based test techniques [4]. Meanwhile, numerous calibration methods have also been presented such as closed-loop and open-loop methods [5], which monitor the deviation in a control voltage for tuning multi-frequency-range VCOs.…”

Section: Introductionmentioning

confidence: 99%

A low-jitter supply-regulated charge pump phase-locked loop with built-in test and calibration

San-Um

Tachibana

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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This paper presents a charge pump phase-locked loop with an integrated power supply regulation. Two independent regulators are employed in order to provide low-sensitivity supply voltages with inherent noise suppression for analog blocks, and to afford multiple reference voltages for test and calibration process. The built-in pre-screening test and calibration system based on the deviation of a control voltage during locking state facilitates on-chip accessibility and observability. Demonstrations of a 200-MHz charge pump phase-locked loop in 0.18-μm CMOS standard technology demonstrate low-jitter and low supply sensitivity performances with test and calibration functionality.

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Motivations towards BIST and DfT for embedded charge-pump phase-locked loop frequency synthesisers

Cited by 10 publications

References 11 publications

A Hybrid Low-Cost PLL Test Scheme based on BIST Methodology

A Hybrid Low-Cost PLL Test Scheme based on BIST Methodology

Closed-loop Built in Self Test for PLL production testing with minimal tester resources

A low-jitter supply-regulated charge pump phase-locked loop with built-in test and calibration

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