MRAM defect analysis and fault modeling

Su, Chao‐Ton; Huang, Rei-Fu; Wu, Cheng‐Wen; Hung, Chien‐Ching; Kao, Ming-Jer; Chang, Yanhong; Wu, Wen-Ching

doi:10.1109/test.2004.1386944

Cited by 11 publications

(9 citation statements)

References 21 publications

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“…STT-MRAM testing is still an on-going research topic. Several fault models such as multi-victim, kink, and write destructive faults [7,8] were proposed for field-driven MRAMs. However, these fault models are not applicable to currentdriven STT-MRAMs.…”

mentioning

confidence: 99%

Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs

Rao

Taouil

et al. 2020

2020 IEEE International Test Conference (ITC)

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Understanding the manufacturing defects in magnetic tunnel junctions (MTJs), which are the data-storing elements in STT-MRAMs, and their resultant faulty behaviors are crucial for developing high-quality test solutions. This paper introduces a new type of MTJ defect: synthetic anti-ferromagnet flip (SAFF) defect, wherein the magnetization in both the hard layer and reference layer of MTJ devices undergoes an unintended flip to the opposite direction. Both magnetic and electrical measurement data of SAFF defect in fabricated MTJ devices is presented; it shows that such a defect reverses the polarity of stray field at the free layer of MTJ, while it has no electrical impact on the single isolated device. The paper also demonstrates that using the conventional fault modeling and test approach fails to appropriately model and test such a defect. Therefore device-aware fault modeling and test approach is used. It first physically models the defect and incorporate it into a Verilog-A MTJ compact model, which is afterwards calibrated with silicon data. The model is thereafter used for fault analysis and modeling within an STT-MRAM array; simulation results show that a SAFF defect may lead to a transient passive neighborhood pattern sensitive fault (tPNPSF) when all neighboring cells are in logic '1' state. Finally, test solutions for such fault are discussed.Index Terms-Device-aware test, STT-MRAMs, manufacturing defects, fault models• Discover a new STT-MRAM-specific defect based on silicon measurements; the defect is referred to as SAFF. • Present magnetic and electrical characterization of MTJ devices with the SAFF defect.

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confidence: 99%

Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs

Rao

Taouil

et al. 2020

2020 IEEE International Test Conference (ITC)

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“…Conventionally, MTJ-related defects irrespective of their physical natures are modeled as linear resistors either in series with (i.e., OC t in Table 4) or in parallel (i.e., S1 BL-IN in Table 5) to an idea defect-free MTJ device, as can be found in [8][9][10][11][12][13]. Comparing the fault modeling results of our proposed pinhole defect model (PH) with the series resistor model OC t and the parallel resistor model S1 BL-IN reveals the following.…”

Section: Pinhole Defects In Mtj Devicesmentioning

confidence: 99%

“…Testing STT-MRAMs is still an emerging research topic. Azevedo et al [8,9] injected resistive shorts and opens into a SPICE model of an MRAM cell and subsequently performed simulations to derive fault models. Su et al [10] did intensive analysis of the excessive magnetic field during write operations and observed write disturbance faults; they validated those using chip measurements.…”

Section: Introductionmentioning

confidence: 99%

Defect and Fault Modeling Framework for STT-MRAM Testing

Rao

Taouil

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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STT-MRAM mass production is around the corner as major foundries worldwide invest heavily on its commercialization. To ensure high-quality STT-MRAM products, effective yet cost-efficient test solutions are of great importance. This paper presents a systematic device-aware defect and fault modeling framework for STT-MRAM to derive accurate fault models which reflect the physical defects appropriately, and thereafter optimal and high-quality test solutions. An overview and classification of manufacturing defects in STT-MRAMs are provided with an emphasis on those related to the fabrication of magnetic tunnel junction (MTJ) devices, i.e., the data-storing elements. Defects in MTJ devices need to be modeled by adjusting the affected technology parameters and subsequent electrical parameters to fully capture the defect impact on both the device's electrical and magnetic properties, whereas defects in interconnects can be modeled as linear resistors. In addition, a complete single-cell fault space and nomenclature are defined, and a systematic fault analysis methodology is proposed. To demonstrate the use of the proposed framework, resistive defects in interconnect and pinhole defects in MTJ devices are analyzed for a single 1T-1MTJ memory cell. Test solutions for detecting these defects are also discussed.

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“…The resistance value represents the defect strength. This approach is also inherited to test emerging non-volatile memories such as STT-MRAM, as can be found in the prior art [8][9][10][11]17]. For any defect in the MTJ device, it is modeled as a linear resistor either in parallel to (R pd ) or in series with (R sd ) a defect-free MTJ model, as illustrated in Fig.…”

Section: Limitations Of Conv Test Approachmentioning

confidence: 99%

“…STT-MRAM testing is still an on-going research topic. Several fault models such as multi-victim, kink, and write destructive faults [8,9] were proposed for field-driven MRAMs. However, these fault models are not applicable to current-driven STT-MRAMs.…”

mentioning

confidence: 99%

Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAM

Wu¹,

Rao²,

Taouil³

et al. 2021

Preprint

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<div>The manufacturing process of STT-MRAM requires unique steps to fabricate and integrate magnetic tunnel junction (MTJ) devices which are data-storing elements. Thus, understanding the defects in MTJs and their faulty behaviors are paramount for developing high-quality test solutions. This article applies the advanced device-aware test to intermediate (IM) state defects in MTJ devices based on silicon measurements and circuit simulations. An IM state manifests itself as an abnormal third resistive state, which differs from the two bi-stable states of MTJ. We performed silicon measurements on MTJ devices with diameter ranging from 60nm to 120nm; the results show that the occurrence probability of IM state strongly depends on the switching direction, device size, and bias voltage. We demonstrate that the conventional resistor- based fault modeling and test approach fails to appropriately model and test such a defect. Therefore, device-aware test is applied. We first physically model the defect and incorporate it into a Verilog-A MTJ compact model and calibrate it with silicon data. Thereafter, this model is used for a systematic fault analysis based on circuit simulations to obtain accurate and realistic faults in a pre-defined fault space. Our simulation results show that an IM state defect leads to intermittent write transition faults. Finally, we propose and implement a device-aware test solution to detect the IM state defect.</div>

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MRAM defect analysis and fault modeling

Cited by 11 publications

References 21 publications

Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs

Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs

Defect and Fault Modeling Framework for STT-MRAM Testing

Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAM

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