Multiple-Gate CMOS Thin-Film Transistor With Polysilicon Nanowire

Im, Maesoon; Han, Jin−Woo; Lee, Hyunjin; Yu, Lee-Eun; Kim, Sungho; Kim, Chang Hoon; Jeon, Sang Cheol; Kim, Kwang Hee; Lee, Gi Sung; Oh, Jae Sub; Park, Yun Chang; Lee, Hee Mok; Choi, Yang‐Kyu

doi:10.1109/led.2007.911982

Cited by 64 publications

(21 citation statements)

References 16 publications

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“…The SS is expected to reduce further as a thinner gate dielectric is used, while the ON current can be further improved by scaling the channel length. These trends were actually observed in a recent report [9]. It is also interesting to see that the drain current under DG mode is larger compared to the counterpart of the SG mode.…”

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confidence: 82%

A Novel Multiple-Gate Polycrystalline Silicon Nanowire Transistor Featuring an Inverse-T Gate

Lin

Hsu

et al. 2008

IEEE Electron Device Lett.

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A novel multiple-gate field-effect transistor with poly-Si nanowire (NW) channels is proposed and fabricated using a simple process flow. In the proposed structure, poly-Si NW channels are formed with sidewall spacer etching technique, and are surrounded by an inverse-T gate and a top gate. When the two gates are connected together to drive the NW channels, dramatic performance enhancement as compared with the cases of singlegate operation is observed. Moreover, subthreshold swing as low as 103 mV/dec at Vd = 2 V is recorded. Function of using the top gate bias to modulate the threshold voltage of device operation driven by the inverse-T gate biases is also investigated in this letter.Index Terms-Field-effect transistor, multiple gate (MG), nanowire (NW), poly-Si. R ECENTLY, we proposed a new field-effect transistor structure which utilizes poly-Si nanowire (NW) as the channels [1], [2]. Fabrication of such device is very simple and requires no advanced lithography tools to generate the nanoscale patterns. Nevertheless, the fine-grain structure of poly-Si NW is considered to affect the carrier transport and device performance. Several ways are possible to relax such concern. One of that is to enhance the film crystallinity by implementing available schemes such as metal-induced lateral crystallization in the fabrication [3]. An alternative strategy is the adoption of multiple-gated (MG) configuration to increase the gate controllability over the channel. This has been widely demonstrated in the literature for devices with doublegate (DG) [4] and triple-gate [5], as well as surrounding-gate schemes [6]. Since poly-Si NWs are with a tiny volume and, thus, a limited amount of defects are contained, MG configuration is also expected to significantly improve the performance of poly-Si NW devices performance. The MG configuration may consist of several separate gates and each gate can be biased independently. Such design allows more freedoms for device operation [7].In this letter, a new MG structure which consists of an inverse-T-gate and a top-gate employed to surround the polySi NW channels is proposed. Top and cross-sectional views of the structure are shown in Fig. 1. From the figure, it can be understood that the poly-Si NW channels are almost fully surrounded by an inverse-T gate and a top gate. Moreover, the two gates can be biased independently to operate the device. Fig. 1. (a) Top and (b) cross-sectional views of the proposed MG FET device with poly-Si NW channels surrounded by an inverse-T gate and a top gate.Schematic flow of the fabrication process for the proposed device is shown in Fig. 2. First, silicon wafers were capped with a 100-nm-thick wet oxide. After depositing a 150-nm-thick in situ-doped n + poly-Si, the inverse-T gate was fabricated by twice standard G-line lithography and dry etching steps [ Fig. 2(a) and (b)]. This was followed by the deposition of a 20-nm-thick low-pressure chemical vapor deposition (LPCVD) oxide layer serving as the dielectric of inverse-T gate. A 100-nm-thick amorphous-...

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confidence: 82%

A Novel Multiple-Gate Polycrystalline Silicon Nanowire Transistor Featuring an Inverse-T Gate

Lin

Hsu

et al. 2008

IEEE Electron Device Lett.

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“…Poly-Si TFTs utilizing a NW channel with multiple-gate structures have been demonstrated to meet demands in electrical characteristics. [5][6][7][8][9][10][11] However, as the gate length of devices narrows down to the nanometer region, short-channel effects (SCEs) such as off-state leakage, and drain-induced barrier lowering (DIBL) increasingly become unavoidable technical challenges. [12][13][14][15][16][17] Moreover, the control of dopant diffusion in the channel during activation at high temperature becomes more difficult if a lightly doped drain process is not adopted.…”

confidence: 99%

Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels

Tso¹,

Liu²,

Sheu³

2015

Jpn. J. Appl. Phys.

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Polycrystalline silicon (poly-Si) nanowire (NW) junctionless (JL) thin-film transistors composed of gate-all-around (GAA) and multiple channels were demonstrated and characterized. The high surface-to-volume ratio of the NW and a nominal gate length of 0.25 µm lead to a clear improvement in electrical performance, including a steep subthreshold swing (SS; >124 mV/decade), a virtual absence of drain-induced barrier lowering (DIBL; 21 + 13 mV/V), and a high I ON /I OFF current ratio (>1 ' 10 9 ) under a relatively low voltage condition (V D = 0.3 V, V G = 5 V), resulting from the multiple-channel structure and small grain boundaries and defects under the gate area.

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“…As the device size is continuously scaled down, the formation of extremely abrupt junctions between source/drain and channel regions is still very challenging, even for the nanowire FETs when operating in the inversion‐mode regime. But still, an ultrathin and narrow body (nanowire) metal‐oxide semiconductor field‐effect transistor, when combined with the gate‐all‐around (GAA) structure, is deemed to be a major candidate for extreme complementary metal‐oxide semiconductor scaling, provided that the process complexities such as fabrication of short wires and the gate definition under the body are solved . To go below 10 nm, GAA transistors are seen as a best option.…”

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confidence: 99%

Numerical modeling of process parameters on RF metrics in FinFETs, junctionless, and gate‐all‐around devices

Lakshmi

Srinivasan²

2016

Int J Numerical Modelling

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This paper deals with the effect of structural, doping, and work function parameter variations on the Radio‐Frequency metrics, unity gain cutoff frequency (ft), non‐quasi static delay, intrinsic gain, and noise figure in double‐gate Fin Field Effect Transistor (FinFET), junctionless FinFETs, and conventional and junctionless gate‐all‐around devices using Technology Computer‐Aided Design simulations. This is done quantitatively by performing a simple sensitivity study experiment and screening analysis through Plackett‐Burman's design of experiment approach. The individual and overall rankings of the input parameters for the devices considered are given. Gate length affects FinFETs significantly, whereas it does not affect junctionless devices. The impact of work function on the output responses is more in junctionless devices compared with that of FinFET and gate‐all‐around devices. Ovality in gate‐all‐around devices has no impact on all the output responses.

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Multiple-Gate CMOS Thin-Film Transistor With Polysilicon Nanowire

Cited by 64 publications

References 16 publications

A Novel Multiple-Gate Polycrystalline Silicon Nanowire Transistor Featuring an Inverse-T Gate

A Novel Multiple-Gate Polycrystalline Silicon Nanowire Transistor Featuring an Inverse-T Gate

Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels

Numerical modeling of process parameters on RF metrics in FinFETs, junctionless, and gate‐all‐around devices

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