Non-uniform clock mesh optimization with linear programming buffer insertion

Guthaus, Matthew R.; Wilke, Gustavo; Reis, Ricardo

doi:10.1145/1837274.1837295

Cited by 27 publications

(32 citation statements)

References 11 publications

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“…Depending on the position of PST buffers in a clock tree, skew may be varied between two flip-flops or two clock groups. A number of algorithms have been proposed in literature to optimize insertion of PST buffers based on statistical timing analysis to maximize binning yield and minimize area/power overhead [5][6][7][8]. In [6], Khandelwal et.…”

Section: Introductionmentioning

confidence: 99%

Variation Aware Design of Post-Silicon Tunable Clock Buffer

Suresh

Burleson

2014

2014 IEEE Computer Society Annual Symposium on VLSI

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Process variation is a major limiting factor in designing high performance circuits in advanced CMOS technologies. Over optimizing data paths to provide adequate design margin is leading to increased area and power overhead. In this work, we present a variation aware design of Post-Silicon Tunable (PST) clock buffers to redistribute clock skew and mitigate impact of process variation on chip performance. Conventional PST buffers are designed for linear delay values. We estimate a set of non-linear delay intervals of PST buffer based on slack variation in each critical path. The configuration device sizes are mapped to the non-linear delay intervals using a set of equality conditions and solved using Linear Programming (LP). The variation aware device sizing provides many small delay intervals within one standard deviation of slack distribution and fewer large delay intervals to compensate for larger slack variations. This helps in optimal tuning of PST buffers to fix hold time, as well as better skew distribution to achieve maximum possible performance in a chip. The proposed PST buffer design technique was implemented for ISCAS'89 benchmark circuits. Non-linear delay PST buffers improve performance binning yield by more than 4%. They also provide optimum buffer circuits with an area reduction of 30% and leakage power reduction of 20%. The proposed technique can be implemented by designing dedicated buffers for each critical path or using a smaller set of pre-designed buffers with non-linear delay values.

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Section: Introductionmentioning

confidence: 99%

Variation Aware Design of Post-Silicon Tunable Clock Buffer

Suresh

Burleson

2014

2014 IEEE Computer Society Annual Symposium on VLSI

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“…The low global clock skew is achieved at the expense of high power consumption compared to tree or other structures because of the excessive wires (mesh grid and stub wires) and buffers used as well as the short circuit power introduced. Due to the popularity of clock mesh in very large scale microprocessors, design automation efforts are made in the area of clock mesh synthesis and optimization [2,10,13,18,22]. In [22], buffer driver insertion and sizing are studied as well as the mesh reduction for power savings.…”

Section: Introductionmentioning

confidence: 99%

“…A uniform clock mesh is assumed in these works in [13,18,22]. In [2] and [10], non-uniform clock meshes are explored in order to reduce mesh wirelength and the power consumption. In [2], the timing delays of the combinational logic paths are considered when building the clock mesh such that the grid density can be adjusted based on the timing criticality.…”

Section: Introductionmentioning

confidence: 99%

Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis

Mao

Taşkın

2011

Proceedings of the 2011 International Symposium on Physical Design

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A novel clock mesh network synthesis approach is proposed in this paper which generates an improved mesh size with registers placed incrementally considering the timing slack on the data paths and the non-uniform grid wire placement. The primary objective of the method is to reduce the power dissipation without a global skew degradation, which is achieved through a sparse and non-uniform mesh implementation with registers incrementally placed in close vicinity to the mesh grids. The incremental register placement is based on the timing information in order to preserve the timing slack of the circuit. Experimental results show that the total wirelength (mesh grid wires and stub wires) as well as the power dissipation is reduced significantly on the clock mesh network. Specifically, the wirelength of the mesh network and the power dissipation of the clock network are reduced by 52% and 48% on average, respectively. Moreover, the global clock skew and the non-negative timing slack are preserved.

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“…[7], [19] do not take non-uniform sink distribution and different clock domains into consideration upfront, resorting to post-processing step (e.g., mesh reduction), which may result in a sub-optimal clock mesh. In all previous work, a sink taps the nearest clock mesh segment, which is not necessarily the best decision when taking uneven sink capacitance distribution and buffering blockages into the account.…”

Section: Introductionmentioning

confidence: 99%

Novel binary linear programming for high performance clock mesh synthesis

Cho

Pan

Puri

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Clock mesh is popular in high performance VLSI design because it is more robust against variations than clock tree at a cost of higher power consumption. In this paper, we propose novel techniques based on binary linear programming for clock mesh synthesis for the first time in the literature. The proposed approach can explore both regular and irregular mesh configurations, adapting to non-uniform load capacitance distribution. Our synthesis consists of two steps: mesh construction to minimize total capacitance and skew, and balanced sink assignment to improve slew/skew characteristics. We first show that mesh construction can be analytically formulated as binary polynomial programming (a class of nonlinear discrete optimization), then apply a compact linearization technique to transform into binary linear programming, significantly reducing computational overhead. Second, our balanced sink assignment enables a sink to tap the least loaded mesh segment (not the nearest one) with another binary linear programming which reduces both slew and skew. Experiments show that our techniques improve the worst skew and total capacitance by 14% and 15% over the state-of-the-art clock mesh algorithm [19] on ISPD09 benchmarks.

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Non-uniform clock mesh optimization with linear programming buffer insertion

Cited by 27 publications

References 11 publications

Variation Aware Design of Post-Silicon Tunable Clock Buffer

Variation Aware Design of Post-Silicon Tunable Clock Buffer

Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis

Novel binary linear programming for high performance clock mesh synthesis

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