Novel approach for precise control of oxide thickness

Saki, K.; Kawase, Susumu; Shiozawa, J.; Yamamoto, Akio; Mikata, Y.

doi:10.1109/issm.2001.963013

Cited by 3 publications

(2 citation statements)

References 3 publications

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“…Fluctuations in oxidation process parameters are crucial factors in gate oxide thickness t ox variation [14] resulting in C ox variation, where C ox is one of the key factors in MOS transistor 1/f noise model [12]. t ox is involved not only in C ox and S idj (f) calculation but also in computation of dynamic transistor parameters (r ds , g m ) and effective channel length L eff for MOSFET in saturation.…”

Section: Results Of Numerical Analysis and Discussionmentioning

confidence: 99%

Dependence of DGMOSFET 1/f Noise on Transistor Geometry and Technology Parameters

Videnović-Mišić

Jevtic²

2006 25th International Conference on Microelectronics

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In this paper theoretical study of a dual-gate MOSFET (DGMOSFET) 1/f noise and its sensitivity to variation of transistor geometry and technology parameters is presented. Expression for 1/f current noise spectral density S id (f) is obtained using an ac current approach in a DGMOSFET LF small-signal noise equivalent circuit. The results show 1/f S id (f) level increase with L 1 increase and W decrease. For a single MOS transistor and L increase opposite 1/f noise behaviour is observed. In case of a DGMOSFET, not only transistors noise sources influence overall noise but also dynamic transistors parameters and load resistance R L . Sensitivity of S id (f) to source/drain junction depth x j is minimal as a consequence of "long channel" DGMOSFET structure. As for oxide thickness, 1/f noise level show expected increase with t ox increase.

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Section: Results Of Numerical Analysis and Discussionmentioning

confidence: 99%

Dependence of DGMOSFET 1/f Noise on Transistor Geometry and Technology Parameters

Videnović-Mišić

Jevtic²

2006 25th International Conference on Microelectronics

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“…variation. New oxidation control systems have been fabricated to take such environmental parameters into account, and thcrefore the oxidation time is controlled [2]. Furthermore, such thin oxide layers cause leakage effects that cannot be further considered as secondary effects.…”

Section: Introductionmentioning

confidence: 99%

Impact of oxide thickness on performances of logic circuits: a predictive simulation study

Frustaci

Corsonello

International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005.

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di Rende -87036 Rende (CS) ITALY I gate (A) I supply (A) I total (A)Abstract -This paper investigates the role that the gate oxide thickness (Tor) plays on. power and deIay behaviors of logic circuits. Static and dynamic CMOS logic gates have been considered as benchmarks. To extend the predictive simulation study here presented to future technologies, Berkeley Predictive Technology Models (BF'TM) have been used. From a circuit perspective, simulation results showed that the optimal Ton is larger than the nominal value, usually obtained from a device perspective.

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