Novel Epitaxial Nickel Aluminide-Silicide with Low Schottky-Barrier and Series Resistance for Enhanced Performance of Dopant-Segregated Source/Drain N-channel MuGFETs

Lee, R.T.P.; Liow, Tsung-Yang; Tan, Kian-Ming; Lim, Andy Eu-Jin; Ho, C. S.; Hoe, Keat-Mum; Lai, M.Y.; Osipowicz, T.; Lo, Guo‐Qiang; Samudra, Ganesh S.; Chi, Dongzhi; Yeo, Yee-Chia

doi:10.1109/vlsit.2007.4339746

Cited by 8 publications

(7 citation statements)

References 2 publications

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“…Hence a full in-situ process, from metal deposition to metal anneals, will be required for low workfunction materials. To overcome this issue, additive doping into NiSi to alter its workfunction has been developed 114,115,116 . This doping is achieved by adding small amounts of low workfunction materials into Ni prior to metal silicidation, which forms an alloyed Ni-based metal silicide, which in turn has a modified workfunction and is resistant to oxidation.…”

Section: (A) (B)mentioning

confidence: 99%

Scaling Challenges for Advanced CMOS Devices

Jacob

Xie

Sung

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

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The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

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Section: (A) (B)mentioning

confidence: 99%

Scaling Challenges for Advanced CMOS Devices

Jacob

Xie

Sung

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

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“…Dopant segregation with metal silicidation provides a practical solution for adjusting Schottky barrier distribution 3 Author to whom any correspondence should be addressed. while using conventional CMOS technologies [10][11][12][13][14]. During silicidation steps, high doses of implanted dopants are segregated into the channel region to form a thin interfacial layer between the silicide and silicon.…”

Section: Introductionmentioning

confidence: 99%

Dopant-segregated Schottky barrier MOSFETs with an insulated dielectric oxide

Shih

Lin

2010

Semicond. Sci. Technol.

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An insulated dielectric oxide (IDO) is presented for the dopant-segregated Schottky barrier MOSFETs (DS-SBMOS) to suppress the unwanted on-and off-state leakage currents in short-channel DS-SBMOS. The effects of the IDO on DS-SBMOS are investigated using two-dimensional device simulations. Although the dopant segregation technique can efficiently modify a Schottky barrier to improve Schottky barrier MOSFETs, the performance of scaled DS-SBMOS suffers from degraded short-channel behavior and ambipolar conduction from the extension of a heavily doped segregation layer. With sidewall IDO insulators between the heavily doped N+ segregation layer and P+ halo region, band-to-band and ambipolar leakage currents are simultaneously minimized. Thus, an optimal halo can be utilized to control the short-channel effect without any constraints in problematic leakage currents. Using the IDO architecture, DS-SBMOS can be successfully scaled as a promising candidate for next-generation CMOS devices.

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“…Several techniques for improving Schottky barriers have intensively been investigated. They include new metals silicidation [1,2,4,5,8,[10][11][12], the use of SiGe or Ge substrates [13,14] and interfacial layer engineering [15][16][17][18][19][20][21][22]. Among those approaches, dopant segregation (DS) with metal silicidation provides a practical solution for adjusting the Schottky barrier distribution using conventional CMOS technologies [18][19][20][21][22].…”

Section: Introductionmentioning

confidence: 99%

“…They include new metals silicidation [1,2,4,5,8,[10][11][12], the use of SiGe or Ge substrates [13,14] and interfacial layer engineering [15][16][17][18][19][20][21][22]. Among those approaches, dopant segregation (DS) with metal silicidation provides a practical solution for adjusting the Schottky barrier distribution using conventional CMOS technologies [18][19][20][21][22]. The insertion of heavily doped segregation layers can effectively modify the Schottky barriers to increase driving current and suppress ambipolar behavior.…”

Section: Introductionmentioning

confidence: 99%

Device considerations and design optimizations for dopant segregated Schottky barrier MOSFETs

Shih

Yeh

2008

Semicond. Sci. Technol.

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This work thoroughly explores the considerations and optimizations of dopant segregated Schottky barrier MOSFETs (DS-SBMOS) using two-dimensional device simulations. The dependences of the device characteristics on the dopant segregated layer are clarified in the DS-SBMOS. The heavier and wider dopant segregation layer efficiently modifies the Schottky barriers to suppress the off-state ambipolar conduction and simultaneously to enhance the on-state driving current. However, DS-SBMOS devices have slightly worse short-channel effects than conventional MOSFETs, because of additional segregation extensions into the silicon substrate. Importantly, apparent degradations of DS-SBMOS in ambipolar conduction are observed when a thinner gate-insulator or a heavier halo profile is used for the scaled short-channel DS-SBMOS. Dual workfunction gate (DWG) architecture is first proposed to optimize DS-SBMOS by tailoring Schottky barrier distributions through vertical gate engineering. An optimal design of DS-SBMOS devices can be achieved using the DWG structure with enhanced driving current, minimized ambipolar conduction and a suitable short-channel effect as the gate-insulator is scaled down.

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Novel Epitaxial Nickel Aluminide-Silicide with Low Schottky-Barrier and Series Resistance for Enhanced Performance of Dopant-Segregated Source/Drain N-channel MuGFETs

Cited by 8 publications

References 2 publications

Scaling Challenges for Advanced CMOS Devices

Scaling Challenges for Advanced CMOS Devices

Dopant-segregated Schottky barrier MOSFETs with an insulated dielectric oxide

Device considerations and design optimizations for dopant segregated Schottky barrier MOSFETs

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