Novel High Speed and Low Power Single and Double Edge-Triggered Flip-Flops

Aezinia, Fatemeh; Najafzadeh, S.; Afzali-Kusha, Ali

doi:10.1109/apccas.2006.342458

Cited by 9 publications

(9 citation statements)

References 4 publications

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“…There is a work load of 12 transistors on a clock which causes a persistent power consumption even at the condition when input vestiges static. This setback in additionally occurs in SRFF too [11]- [16]. Therefore the aim of the circuit designer is not only reducing the transistor count but also to achieve a circuit that rescue it from clock overloading.…”

Section: Review Of Different Master Slavementioning

confidence: 99%

Performance Analysis of Non-Identical Master Slave Flip Flops at 65nm Node

2019

IJITEE

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This paper presents the performance analysis of the different master slave flip flop reported and comparison of their parameters such as power, area, delay setup time and hold time. To reduce the number of transistor count various logic structure mater slave design have been proposed that results reduction in total area of the flip flop. Advantage and disadvantage of the each flip flop has been discussed. Process corner analysis of all flip flop is also presented at supply voltage of 0.7 volts at 27°C temperature. Percentage reduction in power and speed of operation i.e. frequency are discussed

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Section: Review Of Different Master Slavementioning

confidence: 99%

Performance Analysis of Non-Identical Master Slave Flip Flops at 65nm Node

2019

IJITEE

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“…Another drawback of this design is node C, which floats when clock is equal to Figure 1. Scheme of MHLFF [17].…”

Section: Review Of Previous Pulse Triggered Flip-flopsmentioning

confidence: 99%

Two novel low power and very high speed pulse triggered flip‐flops

Razmdideh

Saneei

2014

Circuit Theory & Apps

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Summary Two novel low power and high‐speed pulse triggered flip‐flops were presented in this paper. Short circuit current was controlled, and race condition between pull‐up and pull‐down branches was removed, which caused reduction of power consumption. On the other hand, the number of stack transistors in the discharging path was reduced which decreased delay of the flip‐flops. The first proposed flip‐flop reduced the number of transistors and the second proposed flip‐flop used conditional data mapping and removed floating node of the first flip‐flop. Post‐layout simulation result showed that the first proposed flip‐flop reduced 21% of power delay product and the second proposed flip‐flop reduced 16% of power delay product in comparison with other flip‐flops in 50% of data switching activities. Copyright © 2014 John Wiley & Sons, Ltd.

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“…But in this structure, because of long path from CLK to Q, the delay between CLK and output is high. To improve speed and power, [13] proposed High Speed Modified Hybrid Latch Flip-Flop (HSMHLFF). The circuit is shown in Fig.…”

Section: Hsmhl Flip Flopmentioning

confidence: 99%

“…HSMHLFF also has 5% lesser power than MHLFF. So [13] proposed a novel low power flip-flop circuit which is faster than the [12] but consumes lesser power. …”

Section: Hsmhl Flip Flopmentioning

confidence: 99%