On-Chip High-Voltage Charge Pump Circuit in Standard CMOS Processes With Polysilicon Diodes

Ker, Ming‐Dou; Chen, Shih-Lun

doi:10.1109/asscc.2005.251689

Cited by 8 publications

(3 citation statements)

References 11 publications

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“…However, the SOI process is more expensive than the bulk CMOS process. The charge pump circuit consisting of the polysilicon diodes, which is fully compatible to the standard bulk CMOS process, may be a good candidate to implement the charge pump circuit without the limitation of the breakdown voltages of the parasitic pn-junctions in the future [27].…”

Section: Discussionmentioning

confidence: 99%

Design of Charge Pump Circuit With Consideration of Gate-Oxide Reliability in Low-Voltage CMOS Processes

Ker

Chen

Tsai

2006

IEEE J. Solid-State Circuits

182

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Abstract-A new charge pump circuit with consideration of gateoxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping efficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit do not exceed the normal oper-

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Section: Discussionmentioning

confidence: 99%

Design of Charge Pump Circuit With Consideration of Gate-Oxide Reliability in Low-Voltage CMOS Processes

Ker

Chen

Tsai

2006

IEEE J. Solid-State Circuits

182

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“…Multiple approaches to design around the N-and P-well breakdown voltages in CMOS processes exist. One approach is to use devices that can be implemented on top of the field oxide as the field oxide has a high breakdown voltage [4], another approach is to use multiple ASICs [5]. It is also possible to use processes that are designed for HV applications such as Silicon On Insulator (SOI) processes which has been the approach in [6], [7], [8].…”

Section: Introductionmentioning

confidence: 99%

Novel Clocking Scheme with Improved Voltage Gain for a Two-Phase Charge Pump Topology

Toft

Jørgensen

2019

2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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This paper presents a novel clocking scheme for the Favrat charge pump topology. The proposed clock scheme achieves an 8 % higher maximum power output and a 12 % higher maximum output voltage than the prior-art clock scheme. The novel clock scheme is part of the development of a very high voltage charge pump for MEMS applications. In this work a 46stage charge pump based on the Favrat charge pump topology has been fabricated in a 180-nm SOI process with a > 200 V breakdown voltage. With an input voltage of 5 V the fabricated charge pump reach an output voltage of 185 V when driven by the proposed clock scheme and loaded with a 2 nA load, the prior-art clock scheme can only reach an output voltage of 165 V with a 2 nA load.

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“…In this work, a variable-output high-voltage charge pump has been designed and simulated using a 0.6µm CMOS process and particular attention has been dedicated for MEMS gyroscope applications. In contrary to previous published designs, this design does not utilize any high-voltage capacitors in the charge pump core [25,26,29,30,33]. Instead, a special clocking scheme is used, in which each stage takes the input clocks from the previous stage and generates the output clocks with a DC offset.…”

mentioning

confidence: 99%

All-pMOS 50-V Charge Pumps Using Low-Voltage Capacitors

Emira

Abdelghany

Elsayed

et al. 2013

IEEE Trans. Ind. Electron.

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Item Type ArticleAuthors Emira, Ahmed; AbdelGhany, M.; Elsayed, M.; Elshurafa, Amro M.; Sedky, S.; Salama, Khaled N.Abstract-In this work, two high-voltage charge pumps are introduced. In order to minimize the area of the pumping capacitors, which dominates the overall area of the charge pump, high density capacitors have been utilized. Nonetheless, these high density capacitors suffer from low breakdown voltage which is not compatible with the targeted high voltage application. To circumvent the breakdown limitation, a special clocking scheme is used to limit the maximum voltage across any pumping capacitor. The two charge pump circuits were fabricated in a 0.6µm CMOS technology with poly0-poly1 capacitors. The output voltage of the two charge pumps reached 42.8V and 51V while the voltage across any capacitor did not exceed the value of the input voltage. Compared to other designs reported in the literature, the proposed charge pump provides the highest output voltage which makes it more suitable for tuning MEMS devices. Index Terms-Charge pump, high voltage, MEMS interface, polarization voltage, DC-DC converters I. INTRODUCTION D ESPITE the continuous demand for reducing the supply voltage and the power consumption of integrated circuits [1, 2], there are some applications that still require high voltage operation, such as MEMS devices, EEPROM programmers [3-8], power switches [9], LCD and line drivers [10]. To meet the high voltage requirement, capacitive charge pumps are used in light load applications, while step-up DC-DC converters are used in heavy load applications [11][12][13][14][15][16][17]. Most of charge pump (CP) topologies in the literature [2,[18][19][20] are based on the Dickson charge pump [21], which is shown in Fig. 1, where the output voltage is given by:where N is the number of stages, V IN is the input voltage, and V ti and V to are the threshold voltages of the i th stage (where i = 1, 2, · · · , N ) and the output stage, respectively. This architecture suffers from the continuous increase in the threshold voltage from stage to stage due to the increase in the bulk-source voltage of M i transistor as i increases. Furthermore, the maximum attainable output voltage is limited by

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On-Chip High-Voltage Charge Pump Circuit in Standard CMOS Processes With Polysilicon Diodes

Cited by 8 publications

References 11 publications

Design of Charge Pump Circuit With Consideration of Gate-Oxide Reliability in Low-Voltage CMOS Processes

Design of Charge Pump Circuit With Consideration of Gate-Oxide Reliability in Low-Voltage CMOS Processes

Novel Clocking Scheme with Improved Voltage Gain for a Two-Phase Charge Pump Topology

All-pMOS 50-V Charge Pumps Using Low-Voltage Capacitors

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