Optimization of tunnel FETs: Impact of gate oxide thickness, implantation and annealing conditions

Leonelli, Daniele; Vandooren, A.; Rooyackers, R.; Gendt, Stefan De; Heyns, MM; Groeseneken, G.

doi:10.1109/essderc.2010.5618408

Cited by 33 publications

(17 citation statements)

References 10 publications

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“…Symmetric (004) RSMs were recorded to assign the RLP of each layer in these TFET structures. Citric acid/hydrogen peroxide (C 6 such that the active layer should always be internally lattice matched in these mixed As and Sb based TFET structures. It has been well established that for C doped III-V materials beyond the doping level of 1 Â 10 19 /cm 3 , substitutional carbon causes the III-V host lattice to contract due to its small tetrahedral covalent radius (0.77 Å ).…”

Section: Certification Of Layers Corresponding To Different X-ray Peaksmentioning

confidence: 99%

“…Together with these effects, higher OFF state leakage (I OFF ) and reduced I ON /I OFF ratio are thus expected for sub-65 nm conventional Si MOSFETs. Recently, interband tunneling field-effect-transistors (TFETs) [1][2][3][4][5][6][7][8][9][10] based on band-to-bandtunneling (BTBT) injection mechanism different from diffusion over a potential barrier have been proposed and studied in order to reduce SS below the diffusion limit of 60 mV/dec and reduce I OFF . Numerical simulation model of TFET devices using carbon nanotube, [1][2][3] Ge, 4 Si, [5][6][7] and III-V 8-10 materials exhibited remarkable higher transistor I ON current and steeper SS.…”

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confidence: 99%

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Role of InAs and GaAs terminated heterointerfaces at source/channel on the mixed As-Sb staggered gap tunnel field effect transistor structures grown by molecular beam epitaxy

Zhu

Jain

Vijayaraghavan

et al. 2012

Journal of Applied Physics

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Articles you may be interested inThe structural, morphological, defect properties, and OFF state leakage current mechanism of mixed As-Sb type-II staggered gap GaAs-like and InAs-like interface heterostructure tunnel field effect transistors (TFETs) grown on InP substrates using linearly graded In x Al 1-x As buffer by molecular beam epitaxy are investigated and compared. Symmetric relaxation of >90% and >75% in the two orthogonal h110i directions with minimal lattice tilt was observed for the terminal GaAs 0.35 Sb 0.65 and In 0.7 Ga 0.3 As active layers of GaAs-like and InAs-like interface TFET structures, respectively, indicating that nearly equal numbers of a and b dislocations were formed during the relaxation process. Atomic force microscopy reveals extremely ordered crosshatch morphology and low root mean square roughness of $3.17 nm for the InAs-like interface TFET structure compared to the GaAs-like interface TFET structure of $4.46 nm at the same degree of lattice mismatch with respect to the InP substrates. The GaAs-like interface exhibited higher dislocation density, as observed by cross-sectional transmission electron microscopy, resulting in the elongation of reciprocal lattice point of In 0.7 Ga 0.3 As channel and drain layers in the reciprocal space maps, while the InAs-like interface creates a defect-free interface for the pseudomorphic growth of the In 0.7 Ga 0.3 As channel and drain layers with minimal elongation along the Dx direction. The impact of the structural differences between the two interface types on metamorphic TFET devices was demonstrated by comparing p þ -i-n þ leakage current of identical TFET devices that were fabricated using GaAs-like and InAs-like interface TFET structures. Higher OFF state leakage current dominated by band-to-band tunneling process due to higher degree of defects and dislocations was observed in GaAs-like interface compared to InAs-like interface where type-II staggered band alignment was well maintained. Significantly lower OFF state leakage current dominated by the field enhanced Shockley-Read-Hall generation-recombination process at different temperatures was observed in InAs-like TFET structure. The fixed positive charge at the source/channel heterointerface influences the band lineup substantially with charge density greater than 1 Â 10 12 /cm 2 and the band alignment is converted from staggered gap to broken gap at $6 Â 10 12 /cm 2 . Clearly, InAs-like interface TFET structure exhibited 4Â lower OFF state leakage current, which is attributed primarily to the impact of the layer roughness, defect properties on the carrier recombination rate, suggesting great promise for metamorphic TFET devices for high-performance, and ultra-low power applications. V C 2012 American Institute of Physics.

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Section: Certification Of Layers Corresponding To Different X-ray Peaksmentioning

confidence: 99%

mentioning

confidence: 99%

Role of InAs and GaAs terminated heterointerfaces at source/channel on the mixed As-Sb staggered gap tunnel field effect transistor structures grown by molecular beam epitaxy

Zhu

Jain

Vijayaraghavan

et al. 2012

Journal of Applied Physics

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“…The effects of RDF, such as an unacceptably large increase in the OFF-state current, have recently been demonstrated in TFETs [16][17][18][19]. The presence of doped source and drain regions in TFETs also necessitates a complex thermal budget due to the need for ion implantation and expensive thermal annealing techniques [20][21][22]. Abrupt junctions are essential for efficient tunneling in TFETs [1,2,7].…”

Section: Introductionmentioning

confidence: 99%

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

Kumar

Janardhanan

2013

IEEE Trans. Electron Devices

565

249

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Abstract-Using calibrated simulations, we report a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept. Without the need for any doping, the source and drain regions are formed using the charge plasma concept by choosing appropriate work functions for the source and drain metal electrodes. Our results show that the performance of the doping-less TFET is similar to that of a corresponding doped TFET. The doping-less TFET is expected to be free from problems associated with random dopant fluctuations. Further, fabrication of doping-less TFET does not require high-temperature doping/annealing processes and therefore, cuts down the thermal budget opening up the possibilities for fabricating TFETs on single crystal silicon-onglass substrates formed by wafer scale epitaxial transfer.

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“…The gate-dielectric thickness scaling predictions are experimentally verified in the FinFET TFET implementation (see Fig. 11) (17). Two different effective gate-dielectric thicknesses are realized by modifying the thickness of the high-k oxide (HfO 2 ) which is ECS Transactions, 33 (6) 363-372 (2010) on top of the interfacial oxide layer.…”

Section: Experimental All-si Tfet Datamentioning

confidence: 99%

(Invited) Boosting the On-Current of Si-Based Tunnel Field-Effect Transistors

Verhulst

Vandenberghe²,

Leonelli³

et al. 2010

ECS Trans.

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Tunnel-FETs (TFETs) have the potential for a sub-60 mV/dec subthreshold swing and therefore allow for scaling the supply voltage beyond the 1 V plateau of metal-oxide-semiconductor FETs (MOSFETs). The latter scaling is a necessary condition for a reduction of the power consumption per transistor. Silicon-based TFETs are the most attractive because they allow for a full re-use of the existing expertise in fabricating silicon MOSFETs. However, the large bandgap of silicon results in low on-currents. Therefore, the incorporation of heterostructures is proposed. In particular, a germanium-source silicon-channel n-TFET and, as complementary p-TFET, an indium(gallium)arsenide-source silicon-channel TFET reach on-currents comparable to MOSFETs. To beat the MOSFET performance and allow ultra-low voltage operation, additional performance boosters are required. We analyze the impact of the device configuration and of heterostructure strain. The former is illustrated with experimental data of all-silicon FinFET-based TFETs.

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Optimization of tunnel FETs: Impact of gate oxide thickness, implantation and annealing conditions

Cited by 33 publications

References 10 publications

Role of InAs and GaAs terminated heterointerfaces at source/channel on the mixed As-Sb staggered gap tunnel field effect transistor structures grown by molecular beam epitaxy

Role of InAs and GaAs terminated heterointerfaces at source/channel on the mixed As-Sb staggered gap tunnel field effect transistor structures grown by molecular beam epitaxy

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

(Invited) Boosting the On-Current of Si-Based Tunnel Field-Effect Transistors

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