Optimum wire sizing of
            <i>RLC</i>
            interconnect with repeaters

El-Moursy, Magdy A.; Friedman, Eby G.

doi:10.1145/764808.764816

Cited by 23 publications

(11 citation statements)

References 12 publications

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“…The additional control logic thus consumes only a small fraction of the total power dissipated in the inter-router links. The repeaters and the wires utilize different metal layers and their area overheads are independent of each other [31]. The area consumed by the repeater stages along a 128-bit link is found to be 32 µm 2 in case of the baseline and 80 µm 2 when all the 8 conventional repeaters along the link are replaced by three-state repeaters.…”

Section: Power and Area Estimation For The Interrouter Linksmentioning

confidence: 99%

iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures

Kodi

Sarathy

Louri

2008

2008 International Symposium on Computer Architecture

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Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the deep sub-micron regime. However, the shrinking feature size limits the performance of NoCs due to power and area constraints. Research into the optimization of NoCs has shown that a reduction in the number of buffers in the NoC routers reduces the power and area overhead but degrades the network performance. In this paper, we propose iDEAL, a low-power area-efficient NoC architecture by reducing the number of buffers within the router. To overcome the performance degradation caused by the reduced buffer size, we propose to use adaptive dual-function links capable of data transmission as well as data storage when required. Simulation results for the proposed architecture show that reducing the router buffer size in half and using the adaptive dualfunction links achieves nearly 40% savings in buffer power, 30% savings in overall network power and about 41% savings in the router area, with only a marginal 1-3% drop in performance. Moreover, the performance in iDEAL can be further improved by aggressive and speculative flow control techniques.

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Section: Power and Area Estimation For The Interrouter Linksmentioning

confidence: 99%

iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures

Kodi

Sarathy

Louri

2008

2008 International Symposium on Computer Architecture

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“…According to the topology of NoC interconnects, the interswitch wire lengths, the number of repeaters and the number of switches can be determined a priori. The power consumption of interswitch links � �� and the power consumption of repeaters are defined by (El-Moursy & Friedman, 2004)…”

Section: Fig 7 Communication Network On Chipmentioning

confidence: 99%

High throughput architecture for high performance NoC

Ghany

El-Moursy²,

Ismail

2009

2009 IEEE International Symposium on Circuits and Systems

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“…Technology scaling trends have also resulted in a significant increase in inductive effects in interconnects [2], [3]. Inductance also impacts the wire width optimization [4]. Inductive and capacitive coupling make interconnect coupling noise significant and cause signal integrity concerns.…”

Section: Introductionmentioning

confidence: 99%

A Comparative Study of Interconnect Circuit Techniques for Energy Efficient On-Chip Interconnects

Venkataiah¹,

Tejaswi²

2015

IJCA

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The aggressive technology scaling in VLSI leads to decrease the size of chip. Such continual miniaturization of VLSI devices has strong impact on interconnects in several ways. Interconnects in high speed applications suffer from crosstalk, signal delay and ground noise, causing degradation of system performance. Thus interconnects are becoming a limiting factor in determining circuit performance. This paper presents a comparative study on different interconnect circuit techniques for on chip interconnects. We have compared different circuit structure by placing on RC and RLC interconnects. In this delay benefit for current sensing increases with an increase in wire width. Unlike repeaters, current sensing does not require placement of buffers along the wire and it eliminates any placement constraints. Out of all these techniques a differential RLC current mode signaling circuit insertion has offered the less amount of energy. All the circuits are simulated and compared different parameters such as power, delay and energy by using micro wind in 45nm technology.

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Optimum wire sizing of RLC interconnect with repeaters

Cited by 23 publications

References 12 publications

iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures

iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures

High throughput architecture for high performance NoC

A Comparative Study of Interconnect Circuit Techniques for Energy Efficient On-Chip Interconnects

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