Partial Reconfiguration of FPGAs for Dynamical Reconfiguration of a Software Radio Platform

Delahaye, Jean-Philippe; Palicot, Jacques; Moy, Christophe; Leray, Pierre

doi:10.1109/istmwc.2007.4299250

Cited by 25 publications

(21 citation statements)

References 7 publications

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“…The authors in [19] and [20] benefit from the PR technique to propose reconfigurable radio systems. PR management is controlled by a microblaze soft processor implemented in FPGA with an Internal Configuration Access Port (ICAP) controller.…”

Section: Reconfigurable Radios Using Prmentioning

confidence: 99%

ARM-FPGA-based platform for reconfigurable wireless communication systems using partial reconfiguration

et al. 2017

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Today, wireless devices generally feature multiple radio access technologies (LTE, WIFI, WIMAX, ...) to handle a rich variety of standards or technologies.These devices should be intelligent and autonomous enough in order to either reach a given level of performance or automatically select the best available wireless technology according to standards availability. On the hardware side, system on chip (SoC) devices integrate processors and field-programmable gate array (FPGA) logic fabrics on the same chip with fast inter-connection. This allows designing software/hardware systems and implementing new techniques and methodologies that greatly improve the performance of communication systems. In these devices, Dynamic partial reconfiguration (DPR) constitutes a well-known technique for reconfiguring only a specific area within the FPGA while other parts continue to operate independently. To evaluate when it is advantageous to perform DPR, adaptive techniques have been proposed. They consist in reconfiguring parts of the system automatically according to specific parameters. In this paper, an intelligent wireless communication system aiming at implementing an adaptive OFDM-based transmitter and performing a vertical handover in heterogeneous networks is presented. An unified physical layer for WIFI-WIMAX networks is also proposed. The system was implemented and tested on a ZedBoard which features a Xilinx Zynq-7000-SoC. The performance of the system is described, and simulation results are presented in order to validate the proposed architecture.

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Section: Reconfigurable Radios Using Prmentioning

confidence: 99%

ARM-FPGA-based platform for reconfigurable wireless communication systems using partial reconfiguration

et al. 2017

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“…Furthermore, a number of articles have been published on using DPR to implement different signal processing algorithms [9,11,13,14]. In particular, [15][16][17] report different approaches for taking advantage of DPR in FIR filter implementations.…”

Section: Background and Related Workmentioning

confidence: 99%

“…The majority of previously reported work on FIR filtering is based on multiply-and-add approaches [14,16,17,22]. In [14], the authors reported a reconfiguration time of 1.5 ms for changing the coefficients and their number on a Virtex-II (74.7 KB bitstream).…”

Section: Comparison With Other Pr Systems For Fir Filteringmentioning

confidence: 99%

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Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic

Llamocca

Pattichis

Vera

2010

International Journal of Reconfigurable Computing

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Dynamic partial reconfiguration (DPR) allows us to adapt hardware resources to meet time-varying requirements in power, resources, or performance. In this paper, we present two new DPR systems that allow for efficient implementations of 1D FIR filters on modern FPGA devices. To minimize the required partial reconfiguration region (PRR), both implementations are based on distributed arithmetic. For a smaller required PRR, the first system only allows changes to the filter coefficient values while keeping the rest of the architecture fixed. The second DPR system allows full FIR-filter reconfiguration while requiring a larger PR region. We investigate the proposed system performance in terms of the dynamic reconfiguration rates. At low reconfiguration rates, the DPR systems can maintain much higher throughputs. We also present an example that demonstrates that the system can maintain a throughput of 10 Mega-samples per second while fully reconfiguring about seventy times per second.

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“…Efficient partial reconfiguration is available in high quality (and thus expensive) FPGA only, and it was not a real issue for prototyping and experimenting new protocols. The reader interested in such platforms may read [5]. We achieve the dynamic choice of transmission by other means presented later.…”

Section: Related Work and Motivationsmentioning

confidence: 99%

A MPSoC Prototyping Platform for Flexible Radio Applications

Hedde

Horrein

Pétrot

et al. 2009

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

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Abstract-Full-fledged software radio platforms are complex and expensive systems, focused on signal processing, and not very suitable for easy development and large scale experimentation. We propose a Multi-Processor System-on-Chip (MPSoC) prototyping platform targeting the support for flexible radio. This platform is fully customizable at every layer of the wireless networking stack, making it easy to prototype new protocols from the radio to the application layers. Our goal was threefold: design an efficient but cheap platform supporting flexible radio, provide support for a full system on the platform so that it can run autonomously, use "standard" components as much as possible and a modular design to ensure fast and simple development and testing to network developers. We rely on a highly modular Field-Programmable Gate Array (FPGA) based architecture. The practical results achieved so far show the effectiveness of the proposed solution in term of flexibility and cost.

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Partial Reconfiguration of FPGAs for Dynamical Reconfiguration of a Software Radio Platform

Cited by 25 publications

References 7 publications

ARM-FPGA-based platform for reconfigurable wireless communication systems using partial reconfiguration

ARM-FPGA-based platform for reconfigurable wireless communication systems using partial reconfiguration

Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic

A MPSoC Prototyping Platform for Flexible Radio Applications

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