PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks

Chan, Catherine S.; Hendry, .; Biberman,; Bergman,; Carloni, Luca P.

doi:10.1109/date.2010.5457114

Cited by 107 publications

(68 citation statements)

References 23 publications

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“…This paper expands upon work that has been published previously [5]. New contributions include: 1) a complete discussion of our proposed design methodology; 2) the modeling of Mach-Zehnder switches in our Photonic Device Library; 3) the expansion of our noise model to handle intra-message crosstalk and receiver noise; and 4) inclusion of serialization/de-serialization (SerDes) power within our power model.…”

Section: Introductionmentioning

confidence: 90%

Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks

Chan

Hendry

Bergman

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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107

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Abstract-Photonic technology is becoming an increasingly attractive solution to the problems facing today's electronic chip-scale interconnection networks. Recent progress in silicon photonics research has enabled the demonstration of all the necessary optical building blocks for creating extremely highbandwidth density and energy-efficient links for on-chip and off-chip communications. From the feasibility and architecture perspective however, photonics represents a dramatic paradigm shift from traditional electronic network designs due to fundamental differences in how electronics and photonics function and behave. As a result of these differences, new modeling and analysis methods must be employed in order to properly realize a functional photonic chip-scale interconnect design. In this paper, we present a methodology for characterizing and modeling fundamental photonic building blocks which can subsequently be combined to form full photonic network architectures. We also describe a set of tools which can be utilized to assess the physical-layer and system-level performance properties of a photonic network. The models and tools are integrated in a novel open-source design and simulation environment. We present a case study of two different photonic networks-on-chip to demonstrate how our improved understanding and modeling of the physical-layer details of photonic communications can be used to better understand the system-level performance impact.Index Terms-Optical communications, optical crosstalk, optical losses, photonic interconnection networks, simulation software, system analysis and design.

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Section: Introductionmentioning

confidence: 90%

Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks

Chan

Hendry

Bergman

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

107

View full text Add to dashboard Cite

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“…The LLMOE framework translates application code into a dependency-based instruction trace, which captures the individual operations performed as well as their interdependencies. By creating an instruction trace interface for PhoenixSim [3], a simulation environment which models both photonic and electronic network components, we were able to accurately model the execution of applications on the proposed architectures. …”

Section: Testing Frameworkmentioning

confidence: 99%

Photonics for HPEC: A Low-Powered Solution for High Bandwidth Applications

Robinson

Hendry

Gleyzer

et al. 2011

Optical Fiber Communication Conference/National Fiber Optic Engineers Conference 2011

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IntroductionWhile Moore's law continues to provide increased processing power, that increase now requires a corresponding increase in energy that is no longer insignificant. This problem will have to be addressed by the high performance computing (HPC) community in general going forward. However, its impacts are being felt immediately in the high performance embedded computing (HPEC) community, where size, weight, and power (SWAP) constraints are typical on platforms such as unmanned air vehicles (UAV), satellites, etc. Here, key applications typically involve signal and image processing (SIP). There is an increasing demand to perform SIP applications both in real time, and within a tight power budget. These applications are growing rapidly, especially in the image domain, where processing requirements grow with the square of data collection ability.

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“…Researchers could utilize the established simulation modules directly, which makes it much easier to issue a simulation. Simulation platforms like PhoenixSim [12] in optical network simulation and Wvsn-model [13] in WSNs simulation. However because of compatibility problems, Wvsn-model is not available for OMNet++4.1.…”

Section: Omnet++41 Network Simulationmentioning

confidence: 99%

An Enhanced Energy Efficiency Tree-Based Hierarchical Routing Based on Additional Connections

Ren¹,

Peng²,

He³

et al. 2017

IJCNS

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Instrumented is defined as a key characteristic in the upcoming smart cites, which demands a higher Wireless Sensor Networks (WSNs) performance. Tree-based Hierarchical Routing (THR) is a routing protocol for WSNs static scenarios. THR hierarchically maps WSN area into a routing tree. However, fixed topology and hierarchical architecture leads to unbalanced energy overhead distribution and inflexible routes selection. To uniformly distribute routing energy overhead, reduce routing hops and extend network life cycle, we designed an enhanced THR routing protocol based on additional connections such as Neighbors, Brothers and Nephews. Based on these connections, three actions were introduced which are Shortcut, Overhead Balancing and Adoption. A simulation for different network loads on OMNet++4.1 is issued, and realized this THR routing in Chipcon SmartRF04®EB embedded boards based on Zigbee in a point-to-point topology. According to the simulation results and experiment data, this proposal obviously improved the latency performance, reduced energy overhead and extended the network's life cycle.

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PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks

Cited by 107 publications

References 23 publications

Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks

Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks

Photonics for HPEC: A Low-Powered Solution for High Bandwidth Applications

An Enhanced Energy Efficiency Tree-Based Hierarchical Routing Based on Additional Connections

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