Power and signal integrity challenges in 3D systems

Abstract

Power/signal delivering network for 2D systems comprising a package and an Integrated Circuit (IC) are design tasks that can be concurrently handled today. Design iterations can be locally carried out in each subsystem part without the need to modify the other one's decisions. This is unfortunately not the case in 2.5D/3D stacked systems. Finer system integration technology, either via Through Silicon Stack (TSS) and/or Through Silicon Interposer (TSI), involves tighter evaluation of the coupling effects in the system-wide PDN impedance and Signal Integrity (SI) characteristics. If these interactions are not properly accounted early in the design cycle, undesired design loop iterations, affecting design productivity is possible. Therefore, new tools and flows incorporating abstracted physical information of the PDN and signal interconnect stack architecture are needed for early design exploration. This paper elaborates on the problems, tool flows and methods necessary to address these challenges for 2.5D/3D stacked systems.

Heterogeneous 2.5D integration on through silicon interposer

“…Over the past few years, a significant research effort has been invested on 2.5D integration technologies encompassing fabrication, assembly, packaging, and design automation tools and electrical design issues such as signal integrity/ power integrity (SI/PI). 13 This review paper attempts to capture the advantages of this technology and reviews major challenges and solutions developed by the industry, IME, and other research institutes.…”

“…The molding layer, with a thermal conductivity of 0.7 W/mK, unfavorably adds to the thermal resistance. For the bare die package, larger power inputs (8-20 W) are supplied to achieve a junction temperature rise [7][8][9][10][11][12][13][14][15][16][17] C to minimize junction temperature error in the Theta JC data reduction. A common problem in Theta JC measurement for the bare die package is the misalignment of the cold plate base with the top of the test die.…”

Through Silicon Capacitor co-integrated with TSV as an efficient 3D decoupling capacitor solution for power management on silicon interposer

“…A major issue in power management comes from chip/package anti-resonance taking place when a parallel LC resonator circuit is formed between on-chip capacitance C FE and package inductance [4]. Figure 2 illustrates a simplified resonator model of a classic circuit including the two previously discussed decoupling capacitor types (C PCB and C FE ) and their associated access inductance (L PCB and L FE ).…”