Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks

Nadeau-Dostie, B.; Takeshita, K.; Cote, J-F

doi:10.1109/test.2008.4700574

Cited by 26 publications

(20 citation statements)

References 10 publications

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“…Some approaches have been proposed in the literature to reduce the PD for combinational LBIST (e.g., [1,3]), while fewer approaches exist for scan-based LBIST [2,6,8,17,18]. The solutions for combinational LBIST in [1,3] modify the internal structure of traditional LFSRs to generate intermediate test vectors.…”

Section: Introductionmentioning

confidence: 99%

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Low-Cost and High-Reduction Approaches for Power Droop During Launch-On-Shift Scan-Based Logic BIST

Omaña

Rossi

Beniamino

et al. 2015

IEEE Trans. Comput.

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obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/).In case of abuse or copyright appearing without permission e-mail repository@westminster.ac.uk Abstract-During at-speed test of high performance sequential ICs using scan-based Logic BIST, the IC activity factor (AF) induced by the applied test vectors is significantly higher than that experienced during its in field operation. Consequently, power droop (PD) may take place during both shift and capture phases, which will slow down the circuit under test (CUT) signal transitions. At capture, this phenomenon is likely to be erroneously recognized as due to delay faults. As a result, a false test fail may be generated, with consequent increase in yield loss. In this paper, we propose two approaches to reduce the PD generated at capture during at-speed test of sequential circuits with scan-based Logic BIST using the Launch-On-Shift scheme. Both approaches increase the correlation between adjacent bits of the scan chains with respect to conventional scan-based LBIST. This way, the AF of the scan chains at capture is reduced. Consequently, the AF of the CUT at capture, thus the PD at capture, is also reduced compared to conventional scan-based LBIST. The former approach, hereinafter referred to as LowCost Approach (LCA), enables a 50% reduction in the worst case magnitude of PD during conventional logic BIST. It requires a small cost in terms of area overhead (of approximately 1.5% on average), and it does not increase the number of test vectors over the conventional scan-based LBIST to achieve the same Fault Coverage (FC). Moreover, compared to three recent alternative solutions, LCA features a comparable AF in the scan chains at capture, while requiring lower test time and area overhead. The second approach, hereinafter referred to as High-Reduction Approach (HRA), enables scalable PD reductions at capture of up to 87%, with limited additional costs in terms of area overhead and number of required test vectors for a given target FC, over our LCA approach. Particularly, compared to two of the three recent alternative solutions mentioned above, HRA enables a significantly lower AF in the scan chains during the application of test vectors, while requiring either a comparable area overhead or a significantly lower test time. Compared to the remaining alternative solutions mentioned above, HRA enables a similar ...

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Section: Introductionmentioning

confidence: 99%

“…To reduce PD at capture in scan-based LBIST, the solutions in [2,6,8,9,17,18] have been proposed. Particularly, in [2] PD is reduced by alternately disabling groups of scan chains during test.…”

Section: Introductionmentioning

confidence: 99%

Low-Cost and High-Reduction Approaches for Power Droop During Launch-On-Shift Scan-Based Logic BIST

Omaña

Rossi

Beniamino

et al. 2015

IEEE Trans. Comput.

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“…Several solutions have been proposed in the literature to reduce PP, thus also PD, for combinational LBIST (e.g., [1,3,6]), while fewer approaches exist for scan-based LBIST [2,8,14]. The solutions for combinational LBIST in [1,3,6] modify the internal structure of traditional LBIST LFSRs to generate intermediate test vectors.…”

Section: Introductionmentioning

confidence: 99%

“…To address the issue of PD reduction during the capture cycles in scan-based LBIST, the solutions in [2,8,14] have been proposed. Particularly, in [2] PD is reduced by alternately disabling groups of scan chains during test.…”

Section: Introductionmentioning

confidence: 99%

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Novel approach to reduce power droop during scan-based logic BIST

Omaña

Rossi

Fuzzi

et al. 2013

2013 18th Ieee European Test Symposium (Ets)

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Abstract-Significant peak power (PP), thus power droop (PD), during test is a serious concern for modern, complex ICs. In fact, the PD originated during the application of test vectors may produce a delay effect on the circuit under test signal transitions. This event may be erroneously recognized as presence of a delay fault, with consequent generation of an erroneous test fail, thus increasing yield loss. Several solutions have been proposed in the literature to reduce the PD during test of combinational ICs, while fewer approaches exist for sequential ICs. In this paper, we propose a novel approach to reduce peak power/power droop during test of sequential circuits with scanbased Logic BIST. In particular, our approach reduces the switching activity of the scan chains between following capture cycles. This is achieved by an original generation and arrangement of test vectors. The proposed approach presents a very low impact on fault coverage and test time, while requiring a very low cost in terms of area overhead.

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Test Strategies for Gated Clock Designs

Keller

Chakravadhanula

2009

Power-Aware Testing and Test Strategies for Low Power Devices

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Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks

Cited by 26 publications

References 10 publications

Low-Cost and High-Reduction Approaches for Power Droop During Launch-On-Shift Scan-Based Logic BIST

Low-Cost and High-Reduction Approaches for Power Droop During Launch-On-Shift Scan-Based Logic BIST

Novel approach to reduce power droop during scan-based logic BIST

Test Strategies for Gated Clock Designs

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