Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM

Samandari-Rad, Jeren; Hughey, Richard

doi:10.1109/access.2016.2521385

Cited by 17 publications

(4 citation statements)

References 73 publications

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“…It can be inferred from the table that the mean read power of the proposed E 2 VR11T cell is 42% and 47% less and the mean read power is less by 24% over 6T/8T, 55%, 40%, and 9% against C6T, ST9T, LP10T, and MET11T cells. The variability (µ/σ) is calculated by dividing the mean by standard deviation to verify the resilience at random variation [42][43][44][45]. It is evident that the variability of the E 2 VR11T cell is 0.0332 for read and 0.0356 for write operations, which is reasonably lower than for other cells.…”

Section: Power Variabilitymentioning

confidence: 99%

Energy-Efficient and Variability-Resilient 11T SRAM Design Using Data-Aware Read–Write Assist (DARWA) Technique for Low-Power Applications

Thirugnanam¹,

Soong

Prabhu

et al. 2023

Sensors

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The need for power-efficient devices, such as smart sensor nodes, mobile devices, and portable digital gadgets, is markedly increasing and these devices are becoming commonly used in daily life. These devices continue to demand an energy-efficient cache memory designed on Static Random-Access Memory (SRAM) with enhanced speed, performance, and stability to perform on-chip data processing and faster computations. This paper presents an energy-efficient and variability-resilient 11T (E2VR11T) SRAM cell, which is designed with a novel Data-Aware Read–Write Assist (DARWA) technique. The E2VR11T cell comprises 11 transistors and operates with single-ended read and dynamic differential write circuits. The simulated results in a 45 nm CMOS technology exhibit 71.63% and 58.77% lower read energy than ST9T and LP10T and lower write energies of 28.25% and 51.79% against S8T and LP10T cells, respectively. The leakage power is reduced by 56.32% and 40.90% compared to ST9T and LP10T cells. The read static noise margin (RSNM) is improved by 1.94× and 0.18×, while the write noise margin (WNM) is improved by 19.57% and 8.70% against C6T and S8T cells. The variability investigation using the Monte Carlo simulation on 5000 samples highly validates the robustness and variability resilience of the proposed cell. The improved overall performance of the proposed E2VR11T cell makes it suitable for low-power applications.

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Section: Power Variabilitymentioning

confidence: 99%

Energy-Efficient and Variability-Resilient 11T SRAM Design Using Data-Aware Read–Write Assist (DARWA) Technique for Low-Power Applications

Thirugnanam¹,

Soong

Prabhu

et al. 2023

Sensors

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“…However, process variation makes technology scaling difficult [3]- [9]. Moreover, technology scaling causes a high leakage power in SRAM and DRAM [10]- [11]. To overcome these limitations, researchers have developed emerging nonvolatile memory devices that have zero-leakage power, high-density, and high-scalability characteristics.…”

Section: Introductionmentioning

confidence: 99%

Comparative Analysis and Energy-Efficient Write Scheme of Ferroelectric FET-Based Memory Cells

Lim

et al. 2021

IEEE Access

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The ferroelectric field-effect transistor (FeFET) is one of the most promising candidates for emerging nonvolatile memory devices owing to its low write energy and high ION/IOFF ratio. For FeFET applications as nonvolatile memory devices, 1FeFET, 1T-1FeFET, 2T-1FeFET, and 3T-1FeFET cells have been proposed. The 1FeFET cell exhibits the highest density but suffers from write disturbance. Although the 1T-1FeFET and 2T-1FeFET cells resolve the write disturbance, they use a write scheme with a negative write voltage (VW), which requires voltage swings of many control signals, leading to a significantly high write energy consumption. The 3T-1FeFET cell uses a write scheme without a negative VW; however, it exhibits the largest area overhead. Although the 1T-1FeFET cell resolves the write disturbance with a small area overhead; however, it exhibits high write energy consumption because of the use of a negative VW. In this paper, to significantly reduce the write energy consumption, we propose a less control signal swing (LCSS) write scheme without using a negative VW. Simulation results indicate that the worst, average, and best cases of the proposed LCSS write scheme can achieve 35%, 66%, and 96% lower write energy consumption, respectively, than the write scheme with a negative VW in the 1T-1FeFET cell. We also identify the available sensing schemes for each FeFET cell in the read operation according to the FeFET threshold voltage distribution.

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“…The SRAM and processor are implemented on the same chip, which means that they share the supply voltage. The energy consumption in the caches is emphasized in [3], [4], which is approximately 12% to 45% of the core energy consumption, depending on the application, according to [3]. Thus, to achieve a low-power operation of the entire chip, it is necessary to reduce energy consumption in not just the processor, but the caches as well.…”

Section: Introductionmentioning

confidence: 99%

“…The significant performance degradation, a critical disadvantage of the dual-rail SRAM, cannot meet the speed requirement of several applications [4] because more cache layers are used, and a high cache performance is required in recent computing systems, such as chip-multiprocessor (CMP) [13].…”

Section: Introductionmentioning

confidence: 99%

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache

et al. 2020

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An embedded level-shifting (ELS) dual-rail SRAM is proposed to enhance the availability of dual-rail SRAMs. Although dual-rail SRAM is a powerful solution for satisfying the increasing demand for low-power applications, the enormous performance degradation at low supply voltages cannot meet the high-performance cache requirement in recent computing systems. The requirement of many level shifters is another drawback of the dual-rail SRAM because it degrades the energy-savings. The proposed ELS dualrail SRAM achieves energy-savings by using a low supply voltage to precharge bitlines while minimizing the performance overhead by appropriately assigning a high-supply voltage to critical circuit blocks with effective level-shifting circuits. The sense amplifier embeds a level-shifting operation, thereby operating with a high supply voltage for a fast sensing operation. The proposed dynamic output buffer resolves the potential static current problem and improves the read delay. The number of level shifters is reduced using a proposed write driver, which conducts level-shifting and write-driving simultaneously. The proposed ELS dual-rail SRAM achieves low-power operation with 71.4% power consumption compared to single-rail SRAM with 72% performance overhead in circuit-level simulation, while the previous hybrid dual-rail SRAM shows 67.8% energy consumption with 270% performance overhead. In architecture-level simulation using Gem5 simulator with SPEC2006 benchmarks, the system with the ELS dual-rail SRAM caches shows, on average, 29% performance improvement compared to that of the system with the hybrid dual-rail SRAM caches.

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Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM

Cited by 17 publications

References 73 publications

Energy-Efficient and Variability-Resilient 11T SRAM Design Using Data-Aware Read–Write Assist (DARWA) Technique for Low-Power Applications

Energy-Efficient and Variability-Resilient 11T SRAM Design Using Data-Aware Read–Write Assist (DARWA) Technique for Low-Power Applications

Comparative Analysis and Energy-Efficient Write Scheme of Ferroelectric FET-Based Memory Cells

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache

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