Reduction of Parasitic Capacitance in Indium‐Gallium‐Zinc Oxide (a‐IGZO) Thin‐Film Transistors (TFTs) without Scarifying Drain Currents by Using Stripe‐Patterned Source/Drain Electrodes

Abstract

A new device structure of oxide thin‐film transistor (TFT) having lower overlap capacitance without scarifying the drain current is proposed. This can be used for high‐speed circuits and high frame rate displays using the conventional TFT manufacturing process. The existence of spreading currents in amorphous indium‐gallium‐zinc oxide (a‐IGZO) TFTs with stripe‐patterned source/drain (S/D) electrodes is demonstrated. The device performances of the a‐IGZO TFTs with various widths of stripe‐patterned S/D electrodes and open spaces between them are compared. The drain currents of the a‐IGZO TFTs are almost same when the width of open space changes from 0 to 10 µm because of the existence of spreading currents. The overlap capacitance between gate and S/D of the a‐IGZO TFTs can be significantly reduced without scarifying drain currents by using stripe‐patterned S/D electrodes. The operation frequency of the ring oscillator made of the TFTs with stripe S/D electrodes with 10 µm open space width is 2.5 times that made of the conventional a‐IGZO TFTs. This spreading current concept can be widely used for the design of oxide TFT array with low RC (resistance capacitance product) delay for high‐speed circuits.

Balanced Performance Improvement of a-InGaZnO Thin-Film Transistors Using ALD-Derived Al2O3-Passivated High-k HfGdOx Dielectrics

“…Due to the high mobility, high optical transparency, and superior large area uniformity, , amorphous indium gallium zinc oxide thin film (α-IGZO) has been regarded as a competitive channel material for oxide-based TFTs. − The driving circuits based on α-IGZO TFTs have demonstrated some satisfactory performance and have been applied in some commercial fields. , Unfortunately, most α-IGZO TFTs based on traditional SiO 2 gate dielectrics work at high operating voltage and high power consumption is required, which seriously limit the application of α-IGZO TFTs in battery-powered portable and wearable electronic devices. Since high-k dielectrics can positively affect the capacitive coupling with the channel layer, and thus correspondingly increase the driving current and lower the operating voltage, considerable efforts have been made to realize highly competitive α-IGZO TFTs using a variety of high-k dielectric materials. − In spite of the promising large dielectric constant, the existing shortcomings for high-k gate dielectrics cannot be ignored.…”

The Impact of Solvents on the Performances of Solution‐Processed Indium Gallium Zinc Oxide Thin‐Film Transistors Using Nitrate Ligands

“…However, in flexible electronic devices, overlap issues originate from the fabrication of thermally and mechanically instable flexible substrates . In this context, solution‐processed MOS as TG device structure is more attractive because it reduces the parasitic capacitance due to the smaller amount of contact resistance between gate and source/drain electrodes, it results in good ohmic behavior, and the dielectric layer over the semiconductor helps to protect the active layer from air exposure …”

“…[7,8] In this context, solution-processed MOS as TG device structure is more attractive because it reduces the parasitic capacitance due to the smaller amount of contact resistance between gate and source/drain electrodes, it results in good ohmic behavior, and the dielectric layer over the semiconductor helps to protect the active layer from air exposure. [9,10] In recent years, several methods are introduced to achieve better performance of oxide TFT using low-temperature annealing processes (<300 C) like microwave annealing, [11] laser annealing, [12] ultraviolet (UV) irradiation, [13] infrared exposure, [14] and high-pressure annealing. [15] These methods use an external source to reduce the process temperature and densify the active layer.…”

Improvement of contact resistance in flexible a-IGZO thin-film transistors by CF4/O2 plasma treatment

“…Although this parameter is linearly dependent on the field-effect mobility and quadratically dependent on the transistor channel length, downscaling of the TFT dimensions will not necessarily result in an increase of ft. Short channel effects, the parasitic overlap capacitance COV and a dominating contact resistance RC limit the device performance [4]. Several efforts have been undertaken to reduce COV, e.g., by self-alignment techniques [10] or stripe-patterned electrodes [11].…”