Register-Transfer Level Digital Design Automation: The Allocation Process

Hafer, Lou; Parker, Alice C.

doi:10.1109/dac.1978.1585172

Cited by 30 publications

(5 citation statements)

References 2 publications

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“…'~ Tseng and Siework5 formulate allocation as a clique partitioning problem, while Hafer and Parker formulate it as a linear-programing problem. 24 Kowalski uses an artificial intelligence approach to a l l~c a t i o n .~~ operational level, which scheduling handles adequately, we must be concerned with concurrency at the system level-for example, the automatic synthesis of pipelines.…”

Section: October 1990mentioning

confidence: 99%

From behavior to structure: high-level synthesis

Camposano

1990

IEEE Des. Test. Comput.

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In this tutorial, the author describes how high-level synthesis bridges the gap between behavioral specifications and hardware structure by automatically generating a circuit description from a netlist. The resulting description can be used for other design automation tools such as logic synthesis and layout. Describing high-level synthesis for synchronous digital hardware, the author explains the steps of the process, which include compilation, transformation, scheduling, and allocation.igh-level synthesis bridges the gap between the high-level behavioral specification of a digital circuit and its structure. As opposed to logic synthesis, which optimizes only combina-H tional logic, high-level synthesis deals with memory elements, the interconnection structure, such a s buses and multiplexers, and the sequential aspects of a design. The behavioral specification aims at describing only the functionality of a circuit, or what the circuit must do. The specification is usually in a sequential or procedural language similar to programming languages such a s C or Pascal-for example, sequential VHDL. Circuit structure, on the other hand, gives strong hints about the circuit's implementation, or how it is built. The structure is described by a netlist, a list of components and their interconnections.The first step in synthesis is to compile a specification into an internal representation. The second step is to apply high-level transformations with the goal of optimizing the behavior. Finally, scheduling and allocation convert the behavior into a structure. Scheduling determines the time at which each operation is executed, while allocation synthesizes the necessary hardware to perform the operations. The structure is then passed to other design tools for logic synthesis. The advantage of high-level synthesis is that behavioral specifications are generally shorter than lower level structural specifications. Thus, they are easier to write, understand, and change. This makes them less error prone and faster to simulate, which makes the design of complex systems easier and allows a considerably shorter design cycle. But, a s is often the case, automation at this level also exacts a price, and we may have to trade advantages for larger or slower hardware. Moreover, design automation cannot generally match the abilities of a skilled human designer. Despite these drawbacks, design automation does increase productivity significantly. ~ DESIGN REPRESENTATIONA requisite for high-level synthesis is the precise definition of circuit behavior and structure and the systematic classification of design representations. As Table 1 shows, this definition and classification commonly involves two orthogonal axes: the domain and the level. There are three domains: the behavioral, the structural, and the physical. Ideally, pure behavior is described in terms of a n input-output relationship, such as a set of Boolean equations for a combinational network. The structure describes the topology of a system and is typically given 0740-7475/90/001...

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Section: October 1990mentioning

confidence: 99%

From behavior to structure: high-level synthesis

Camposano

1990

IEEE Des. Test. Comput.

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“…So far, some tools have been demonstrated for the early part of the design cycle, but the total system is not yet complete [Bar73, Tho77,Sno78,Haf78]. There is also an effort in Japan to develop a system to help a designer translate an existing SSI or MSI implementation into LSI [Nak78].…”

Section: Logic Synthesismentioning

confidence: 99%

A new look at logic synthesis

Darringer

Joyner

1980

Proceedings of the Seventeenth Design Automation Conference on Design Automation - DAC '80

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Despite many attempts to generate hardware implementations automatically from functional specifications, the literature does not record any commercial success. Previous efforts have dealt primarily with technology-independent primitives and have emphasized circuit minimization. However, larger scales of integration have made other design requirements and technology restrictions as important as circuit count, and have increased the cost of making an engineering change. Thus it is becoming increasingly important to insure that initial chip designs are correct. This paper outlines an investigation into the feasibility of logic synthesis in this new context. A system is described which will produce a naive implementation automatically from a functional specification, and then will interact with the designer, allowing him to evaluate it with respect to these many factors, and to improve it incrementally by applying local transformations until it is acceptable for manufacture. The use of simple local transformations will insure correct implementations, will isolate technology-specific data, and will allow the total process to be applied to larger VLSI designs. This approach has been tested on the design of a single chip with encouraging results. A prototype synthesis system is now being used to perform further experiments. Logic SynthesisThe goal of logic synthesis is to accept functional specifications for a hardware unit and to generate automatically a detailed, technology-specific implementation comparable in quality to that of an experienced engineer. The nature of this problem depends on the level of the functional description, the set of implementation primitives, and the criteria of acceptability. Initially, we are examining a restricted form of synthesis. That is, we are concentrating on the problem of generating masterslice implementations from low-level register transfer specifications in which all memory elements are Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the ACM copyright notice and the title of the publication and its date appear, and notice is given that copying is by permission of the Association for Computing Machinery. To copy otherwise, or to republish, requires a fee and/or specific permission. specified. The combinational network between the memory elements must be generated and the entire function must be implemented with primitives from a specified set. Further, the implementation must satisfy given performance requirements and technology restrictions. We hope to determine the feasibility of interactive synthesis in this context, and the applicability of techniques of program analysis and optimization.There has been much work on automating logic design and, although many effective tools have been developed to aid the implementer, synthesis is not considered commercially successful. Early work centered on developing algorithms for translating a boolean function into a minimum two-le...

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“…The use of the PDP-S/F. is n major slop in two ways: 1) It represents about a five fold incroar.e in Ihe circuit complexity over previously reported example designs [8], and 2) It is a commercially available system that has been implemented in various technologies by different manufacturers over several years, fhur, it is possible lo compare a non-trivial automated design lo designs clone by several designers with different logic components.…”

Section: The Pdp-8/e Examplementioning

confidence: 99%

The CMU Design Automation System - An Example of Automated Data Path Design

Parker

Thomas

Siewiorek

et al. 1979

16th Design Automation Conference

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This paper illustrator* tho methodology of the CMU Design Automation System by presenting, an automated design of the PDP-8/E data palhs from a functional description. This automated clnsign (using synthesis techniques) is compared both to DECV, implementation and the Intersil single chip implementation. 1, IntroductionAG it is becoming possible to integrate larger numbers of logic components on a single chip, the need for more powerful design aide is becoming apparent. Indeed, these aids must be capable of supporting a designer from the system level of design clown to I ho mask level. In this way the systems level designer can become more aware of the implications of higher-level design tradeoffs on implementation properties such as silicon area, power consumption, testability, and speed, and ho able to make more timely use of new technologies. The ultimate goal of the Carnegie-Mellon University Design Automation (CMU-DA) System [12] is to provide a technology-relative, structured-design aid to help the hardware designer explore a larger number of possible design implementations.Inputs to the system are a behavioral description of the system to be designed, an objective function which specifics the user's optimization criteria, and a data base specifying the hardware components available to the design system. The CMU-DA system differs from other design automation systems because the input design description is a functional specification. Such a specification provides a model that, while accurately characterizing the input-output behavior desired for the implementation, doer, not necessarily specify its internal structure.Tho The paper will conclude by comparing these two alternative designs to commercial implementations.

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Register-Transfer Level Digital Design Automation: The Allocation Process

Cited by 30 publications

References 2 publications

From behavior to structure: high-level synthesis

From behavior to structure: high-level synthesis

A new look at logic synthesis

The CMU Design Automation System - An Example of Automated Data Path Design

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