Resistive switching characteristics of CMOS embedded HfO2-based 1T1R cells

Walczyk, Damian; Walczyk, Christian; Schroeder, Thomas; Bertaud, T.; Sowińska, M.; Lukosius, M.; Fraschke, Mirko; Tillack, Bernd; Wenger, Christian

doi:10.1016/j.mee.2011.03.123

Cited by 59 publications

(40 citation statements)

References 18 publications

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“…In recent days, resistive random-access memory (RRAM) has attracted attention as a promising candidate for the next-generation non-volatile memory (NVM) due to its superior scalability, high-speed operation, and low power consumption [1][2][3][4][5][6][7][8][9][10][11][12][13] in order to overcome the limitations such as scaling issues of conventional memories [14,15]. There can be a number of resistive switching mechanisms classified into thermo-chemical, valence-change, and electro-chemical effects depending on the material properties of electrode and resistive switching layer [1].…”

Section: Introductionmentioning

confidence: 99%

“…There can be a number of resistive switching mechanisms classified into thermo-chemical, valence-change, and electro-chemical effects depending on the material properties of electrode and resistive switching layer [1]. Also, it has been reported that RRAM device based on electrochemical metallization mechanism is particularly suitable for embedded NVM applications by adopting 1-transistor 1-resistor (1T1R) configuration due to its fast switching speed and low switching voltage [12,13]. RRAM devices based on conventional metal-insulator-metal (MIM) structure have been widely researched, whereas metal-insulator-silicon (MIS) structure which can be integrated with CMOS circuits (the easiness is improved if 1T1R structure is adopted) has been seldom studied so far [5,6,9].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Effect of Bottom Electrode on Resistive Switching Voltages in Ag-Based Electrochemical Metallization Memory Device

Kim¹,

Cho²,

Park³

2016

JSTS:Journal of Semiconductor Technology and Science

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Effect of Bottom Electrode on Resistive Switching Voltages in Ag-Based Electrochemical Metallization Memory Device

Kim¹,

Cho²,

Park³

2016

JSTS:Journal of Semiconductor Technology and Science

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“…17 Hence, in this work, we focus on understanding the chemical and electronic modifications that occur during this first electroforming process on CMOS-compatible Ti/HfO 2 /TiN RRAM cells. 18 For this purpose, a Ti/HfO 2 /TiN thin film system was prepared on an 8 in. (001)-oriented Si wafer.…”

mentioning

confidence: 99%

Hard x-ray photoelectron spectroscopy study of the electroforming in Ti/HfO2-based resistive switching structures

Sowińska¹,

Bertaud²,

Walczyk³

et al. 2012

Applied Physics Letters

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100

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Study of polarity effect in SiOx-based resistive switching memory Appl. Phys. Lett. 101, 052111 (2012) Ambipolar operation of hybrid SiC-carbon nanotube based thin film transistors for logic circuits applications Appl. Phys. Lett. 101, 043121 (2012) Non-volatile memory transistor based on Pt nanocrystals with negative differencial resistance J. Appl. Phys. 112, 024319 (2012) Resistive switching by migration of hydrogen ions Appl. Phys. Lett. 101, 043507 (2012) Controllable formation of resistive switching filaments by low-energy H+ irradiation in transition-metal oxides

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“…Additionally, the vast majority of memristor materials are not available as part of a standard foundry process. Accordingly, several groups to date have integrated memristors with CMOS on whole wafers or with modifications to the standard foundry process [11], [12], [13], [14], [15], [16], [17], [18]. Because such approaches may be prohibitively expensive without special access to a foundry, it is preferable to use standard foundry CMOS dies and fabricate memristors by postprocessing.…”

Section: Introductionmentioning

confidence: 99%

Vertical integration of memristors onto foundry CMOS dies using wafer-scale integration

Rofeh¹,

Sodhi

Payvand

et al. 2015

2015 IEEE 65th Electronic Components and Technology Conference (ECTC)

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As Moore's law scaling approaches its physical limit, there is increased interest in memristors as a replacement to transistors in memory applications due to their smaller footprint and superior scaling characteristics. However, memristors are intrinsically two-terminal devices, requiring an underlying CMOS control interface for proper operation. Thus the integration of CMOS and memristors is essential to the development of memristor technology. Accordingly, hybrid configurations have been proposed that make use of the advantages of CMOS while utilizing a high density of memristors. However, memristor/CMOS hybrid fabrication is not trivial because high-density memories require memristor dimensions to be much smaller than those of the underlying CMOS. Additionally, memristors typically make use of materials not allowed in conventional CMOS fabrication. These issues point to a post-CMOS fabrication approach. An associated consideration for memristor/CMOS hybrid fabrication is the high cost of whole wafer fabrication. While whole wafer fabrication of memristors is viable for large volume markets, it is not a practical route for niche applications or research. While this suggests the use of CMOS dies, edge effects typically set the minimum processable die size, as in the case of edge beads, which limit the achievable resolution of devices. To address these issues, we present a hybrid integration approach for post-CMOS vertical integration of memristors that is independent of CMOS die size. Our approach enables the vertical integration of memristors with small foundry-fabricated dies using a waferscale integration scheme. We demonstrate this approach using a 2.2-mm × 3.2-mm CMOS die fabricated in a standard dualpoly, three-metal 0.5-µm technology process. We use solution-processed BCB as an adhesive to embed CMOS dies into silicon wafer handles, allowing for easy handling and compatibility with a variety of lithography techniques such as electron-beam, nanoimprint and photolithography. The process is compatible with spin-coated planarization layers, such as polyimide or BCB, if nanometer-scale roughness is desired. As a demonstration, vertically integrated Ag/SiO 2 /Pt switches were fabricated on CMOS using conventional photolithography techniques in a university cleanroom and tested through the CMOS circuitry. The measurements were compared to those of Ag/SiO 2 /Pt switches fabricated off-chip in a similar process and indicate that the memristor/CMOS hybrids were fully functional. We believe this hybrid approach will pave the way for hybrid CMOS-memristor chips, enabling applications from neuromorphic computing to high-density memories.

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Resistive switching characteristics of CMOS embedded HfO2-based 1T1R cells

Cited by 59 publications

References 18 publications

Effect of Bottom Electrode on Resistive Switching Voltages in Ag-Based Electrochemical Metallization Memory Device

Effect of Bottom Electrode on Resistive Switching Voltages in Ag-Based Electrochemical Metallization Memory Device

Hard x-ray photoelectron spectroscopy study of the electroforming in Ti/HfO2-based resistive switching structures

Vertical integration of memristors onto foundry CMOS dies using wafer-scale integration

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