RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs

Cho, Seongjae; Kim, Kyung Rok; Park, Byung‐Gook; Kang, In Man

doi:10.1109/ted.2011.2109724

Cited by 178 publications

(80 citation statements)

References 33 publications

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“…13(a) and (b) demonstrate the capacitance and transconductance of the two different types of devices. C gs and C gd are fixed by oxide and channel surface charges in these devices [21]. As shown in Fig.…”

Section: Comparison With Conventional Bulk Finfetmentioning

confidence: 98%

Design and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors

Kim¹,

Seo²,

Yoon³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-We design and analyze the n-channel junctionless fin-shaped field-effect transistor (JL FinFET) with 10-nm gate length and compare its performances with those of the conventional bulktype fin-shaped FET (conventional bulk FinFET). A three-dimensional (3-D) device simulations were performed to optimize the device design parameters including the width (W fin ) and height (H fin ) of the fin as well as the channel doping concentration (N ch ). Based on the design optimization, the two devices were compared in terms of direct-current (DC) and radio-frequency (RF) characteristics. The results reveal that the JL FinFET has better subthreshold swing, and more effectively suppresses short-channel effects (SCEs) than the conventional bulk FinFET.Index Terms-Junctionless, fin-shaped field-effect transistor (FinFET), short-channel effect (SCE), 3-D device simulation

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Section: Comparison With Conventional Bulk Finfetmentioning

confidence: 98%

Design and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors

Kim¹,

Seo²,

Yoon³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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“…In addition, the radius of the nanowire can readily be reduced to a few nanometres in size that limits the scaling of conventional MOSFET and also because of their adoptability for high-density integration including that of 3D [7,8]. It was also found that gate-all-around (GAA) silicon nanowire transistors (SiNWTs) have cut-off frequency larger than that of planar Si MOSFET [9][10][11]. However, as with many novel device architectures, the SiNW MOSFET has problems of its own.…”

Section: Introductionmentioning

confidence: 99%

Influence of gate metal engineering on small-signal and noise behaviour of silicon nanowire MOSFET for low-noise amplifiers

Gupta

Chaujar

2016

Appl. Phys. A

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In this paper, we have investigated the smallsignal behaviour and RF noise performance of gate electrode workfunction engineered (GEWE) silicon nanowire (SiNW) MOSFET, and the results so obtained are simultaneously compared with SiNW and conventional MOS-FET at THz frequency range. This work examines reflection and transmission coefficients, noise conductance, minimum noise figure and cross-correlation factor. Results reveal significant reduction in input/output reflection coefficient and an increase in forward/reverse transmission coefficient owing to improved transconductance in GEWESiNW in comparison with conventional counterparts. It is also observed that minimum noise figure and noise conductance of GEWE-SiNW is reduced by 17.4 and 31.2 %, respectively, in comparison with SiNW, thus fortifying its potential application for low-noise amplifiers (LNAs) at radio frequencies. Moreover, the efficacy of gate metal workfunction engineering is also studied and the results validate that tuning of workfunction difference results further improvement in device small-signal behaviour and noise performance.

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“…JL MOSFET is getting more attention for its advantages of small drain-induced barrier lowering (DIBL), small subthreshold swing (SS), and low standby power (LSTP) [3][4]. Also it was proven that it has a merit of outstanding maximum oscillation frequency (f max ) [5]. In this work, we characterized GAA JL MOSFETs by 3-dimensional (3D) device simulator.…”

Section: Introductionmentioning

confidence: 99%

“…By this approach, efforts were made for the highest degree of validation that one can expect from a simulation-based research. MOSFETs [5], the proposed NQS model has been comprised in the components of the gate-bias-dependent S/D resistances (R si /R di ) and independent S/D resistances (R se /R de ) that are extracted from a known method [6]. R elect can be extracted by a separate extraction method for gate resistance components [7].…”

Section: Introductionmentioning

confidence: 99%

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Small-Signal Modeling of Gate-All-Around (GAA) Junctionless (JL) MOSFETs for Sub-millimeter Wave Applications

Lee¹,

Cho²,

Park³

et al. 2012

JSTS:Journal of Semiconductor Technology and Science

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RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs

Cited by 178 publications

References 33 publications

Design and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors

Design and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors

Influence of gate metal engineering on small-signal and noise behaviour of silicon nanowire MOSFET for low-noise amplifiers

Small-Signal Modeling of Gate-All-Around (GAA) Junctionless (JL) MOSFETs for Sub-millimeter Wave Applications

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