Runtime Data Management on Non-Volatile Memory-based Heterogeneous Memory for Task-Parallel Programs

Wu, Kai; Ren, Jie; Liu, Dong

doi:10.1109/sc.2018.00034

Cited by 38 publications

(47 citation statements)

References 43 publications

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“…HMS: Work on data placement in HMS have either focused on NVM+DRAM [17,26,34,[52][53][54] or DRAM+HBM systems [41,42,50]. Dulloor et al develop a placement policy where data structures are placed in DRAM based on access patterns on an emulated DRAM+NVM platform [17].…”

Section: Related Workmentioning

confidence: 99%

Intelligent Data Placement on Discrete GPU Nodes with Unified Memory

Sultana

Allen

Qasem

2020

Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques

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With increasing heterogeneity, the importance of data organization within a compute node has grown immensely. Recently, industry vendors have introduced technology that can present a unified shared address space for multiple physical pools of memory. In this paper, we leverage unified memory technology and characterize the performance trade-offs of host and device placement across a range of hybrid application design patterns. We perform a Roofline analysis to establish fundamental performance bounds in collaborative applications and then develop an analytical model that makes profitable placement decisions at the individual data structure level. We integrate the placement model into a runtime system and enable transparent data placement in CUDA/C++ applications. Preliminary experiments yield the following results: (i) placement policies have significant performance impact across hybrid application design paradigms (ii) placement decisions are impacted by the sparsity of data access, page re-migration, amount of latency hiding opportunities and design-specific attributes such as the number of pipeline stages, and (iii) intelligent data placement can improve node performance by up to 5× on applications with sparse access patterns. CCS CONCEPTS • General and reference → Performance; • Software and its engineering → Runtime environments.

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Section: Related Workmentioning

confidence: 99%

Intelligent Data Placement on Discrete GPU Nodes with Unified Memory

Sultana

Allen

Qasem

2020

Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques

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“…Many studies have extensively investigated software techniques for improving application performance on heterogeneous memory systems even before the NVM hardware is available [5,23,34]. These works identify data structures or pages that are critical for performance and manage data placement between dierent memories, either statically or at runtime.…”

Section: Related Workmentioning

confidence: 99%

System evaluation of the Intel optane byte-addressable NVM

Peng

Gokhale

Green

2019

Proceedings of the International Symposium on Memory Systems

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Byte-addressable non-volatile memory (NVM) features high density, DRAM comparable performance, and persistence. These characteristics position NVM as a promising new tier in the memory hierarchy. Nevertheless, NVM has asymmetric read and write performance, and considerably higher write energy than DRAM. Our work provides an in-depth evaluation of the rst commercially available byte-addressable NVM -the Intel Optane R DC TM persistent memory. The rst part of our study quanties the latency, bandwidth, power eciency, and energy consumption under eight memory congurations. We also evaluate the real impact on in-memory graph processing workloads. Our results show that augmenting NVM with DRAM is essential, and the combination can eectively bridge the performance gap and provide reasonable performance with higher capacity. We also identify NUMA-related performance characteristics for accesses to memory on a remote socket. In the second part, we employ two ne-grained allocation policies to control trac distribution between DRAM and NVM. Our results show that bandwidth spilling between DRAM and NVM could provide 2.0x bandwidth and enable 20% larger problems than using DRAM as a cache. Also, write isolation between DRAM and NVM could save up to 3.9x energy and improves bandwidth by 3.1x compared to DRAM-cached NVM. We establish a rooine model to explore power and energy eciency at various distributions of read-only trac. Our results show that NVM requires 1.8x lower power than DRAM for data-intensive workloads. Overall, applications can signicantly optimize performance and power eciency by adapting trac distribution to NVM and DRAM through memory congurations and ne-grained policies to fully exploit the new memory device.

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“…However, these works only combine coarse-grained architecture-supported profiling with low-level (i.e., physical) memory management, and are therefore vulnerable to inefficiencies that arise from the applications working at cross-purposes from the OS and hardware. Unimem [31] also integrates hardware-based profiling with application events, and even adjusts tier assignments dynamically in response to shifting guidance. The adopted MemBrain approach applies static guidance, but unlike Unimem, it does not require any source code modification.…”

Section: Other Related Workmentioning

confidence: 99%

“…The architecture and systems communities are currently exploring how to transcend limitations faced by common hardware-and software-based approaches. Several recent projects have proposed program profiling and analysis tools that augment applications with facilities to guide assignments of data to distinct memory tiers [7,8,10,11,26,27,30,31]. For instance, the MemBrain approach [26] collects profiles of application memory usage and automatically converts them into tier recommendations for each data allocation site.…”

Section: Introductionmentioning

confidence: 99%

Portable application guidance for complex memory systems

Olson¹,

Kammerdiener²,

Jantz³

et al. 2019

Proceedings of the International Symposium on Memory Systems

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The recent emergence of new memory technologies and multi-tier memory architectures has disrupted the traditional view of memory as a single block of volatile storage with uniform performance. Several options for managing data on heterogeneous memory platforms now exist, but current approaches either rely on inflexible, and often inefficient, hardware-based caching, or they require expert knowledge and source code modification to utilize the different performance and capabilities within each memory tier. This paper introduces a new software-based framework to collect and apply memory management guidance for applications on heterogeneous memory platforms. The framework, together with new tools, combines a generic runtime API with automated program profiling and analysis to achieve data management that is both efficient and portable across multiple memory architectures. To validate this combined software approach, we deployed it on two real-world heterogeneous memory platforms: 1) an Intel ® Cascade Lake platform with conventional DDR4 alongside nonvolatile Optane TM DC memory with large capacity, and 2) an Intel ® Knights Landing platform high-bandwidth, but limited capacity, MCDRAM backed by DDR4 SDRAM. We tested our approach on these platforms using three scientific mini-applications (LULESH, AMG, and SNAP) as well as one scalable scientific application (QM-CPACK) from the CORAL benchmark suite. The experiments show that portable application guidance has potential to improve performance significantly, especially on the Cascade Lake platform-which achieved peak speedups of 22x and 7.8x over the default unguided software-and hardware-based management policies. Additionally, this work evaluates the impact of various factors on the effectiveness of memory usage guidance, including: the amount of capacity that is available in the high performance tier, the input that is used during program profiling, and whether the profiling was conducted on the same architecture or transferred from a machine with a different architecture.

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Runtime Data Management on Non-Volatile Memory-based Heterogeneous Memory for Task-Parallel Programs

Cited by 38 publications

References 43 publications

Intelligent Data Placement on Discrete GPU Nodes with Unified Memory

Intelligent Data Placement on Discrete GPU Nodes with Unified Memory

System evaluation of the Intel optane byte-addressable NVM

Portable application guidance for complex memory systems

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