Sandblaster low power DSP [parallel DSP arithmetic microarchitecture]

Abstract

General purpose processors have utilized complex and energy inefficient techniques to accelerate performance. In embedded DSP designs, power constraints have precluded general purpose microarchitectural techniques. Rather than minimize average execution time, embedded DSP processors require the worst case execution time to be minimized. Subsequently, Very Long Instruction Word (VLIW) processors have been employed, but architecturally visible side effects have imposed restrictions on parallelism due to interrupt and latency considerationsparticularly if all loads must complete prior to servicing interrupts. In this paper, we present a low power multithreaded interlocked (transparent) microarchitecture capable of parallelizing non-associative DSP arithmetic. We describe specific memory and logic techniques for reducing power dissipation and discuss how multithreading enables low power optimization.