Selective-area growth of vertically aligned GaAs and GaAs/AlGaAs core–shell nanowires on Si(111) substrate

Abstract

We report on selective-area growth of vertically aligned GaAs nanowires on Si(111) substrate. Modification of the initial Si(111) surface by pretreatment under an AsH(3) atmosphere and low-temperature growth of GaAs were important for controlling the growth orientations of the GaAs nanowire on the Si(111) surface. We also found that the size of openings strongly affected the growth morphology of GaAs nanowires on Si(111). Small diameter openings reduced the antiphase defects and improved the optical properties in the GaAs nanowires. Moreover, we realized coherent growth without misfit dislocation at the GaAs/Si interface. Finally, we demonstrated fabrication of a GaAs/AlGaAs core-shell nanowire array on a Si surface and revealed that the luminescence intensity was markedly enhanced by passivation effects. These results are promising for future III-V nanowire-based optoelectronic integration on Si platforms.

Nanostructure and strain properties of core-shell GaAs/AlGaAs nanowires

“…Previous studies have shown that the GaAs/AlGaAs core-shell NWs grow predominantly as cubic zinc-blende (ZB) single crystals, mainly along the <111> direction, perpendicular to the substrate surface [13,14]. Occasionally, NW segments of hexagonal wurtzite (WZ) structure have been observed to penetrate the ZB structure, as well.…”

“…Occasionally, NW segments of hexagonal wurtzite (WZ) structure have been observed to penetrate the ZB structure, as well. In III-V NWs structural defects, such as rotational twins and stacking faults (SFs) along the growth direction of the NWs are often observed, the latter been responsible for the transition between ZB and WZ structures and viceversa [14,15]. High density of these defects in the nanometer scale may induce a variation of the band gap and influence electron transport along the NWs [15].…”

Current increment of tunnel field-effect transistor using InGaAs nanowire/Si heterojunction by scaling of channel length

“…[5][6][7][8] III-V nanowire/Si heterojunctions with less dislocations have been achieved due to recent progress in epitaxial techniques such as selective-area growth (SAG) regardless of any mismatch in lattice constant and thermal coefficients, which have enabled the integration of III-V NWs on Si with precise positioning and vertical alignment. [9][10][11] This nm-scaled heteroepitaxy has produced inherently abrupt junctions across the III-V nanowire and Si and has demonstrated the potential of steep subthreshold slope (SS) switches using InAs NW/Si heterojunctions. 8,12 Conventional integrated circuits using Si complementary metal-oxide-semiconductor (CMOS) technology are now confronted with a serious problem where a huge amount of power is consumed as integration density increases due to the miniaturization of FETs.…”

Bottom-up engineering of InAs at the nanoscale: From V-shaped nanomembranes to nanowires

“…Nanoscale electronics, optoelectronics, photonics and photovoltaics would benefit from this integration because nanoscale structures could be eventually engineered on silicon, a mature and less expensive platform and with complementary functionality. III-V nanostructures are promising as they offer an efficient elastic relaxation of the strain thanks to their small footprint and freestanding nature [32][33][34].…”