Self-Consistent Modeling of Heating and MOSFET Performance in 3-D Integrated Circuits

Akturk, Akin; Goldsman, N.; Metze, G.

doi:10.1109/ted.2005.857187

Cited by 41 publications

(17 citation statements)

References 19 publications

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“…Due to the stacking of several active layers, which are all sources of power dissipation, the power density of a 3-D chip can be much higher than that of traditional chips. Moreover, the stacked active layers are far away from the heat sink (which is attached to the chip substrate of layer 1) leading to large temperature gradient in the vertical direction [13,14]. Additionally, considering the importance of leakage power dissipation (which is exponentially dependent on temperature) in nanometer scale technologies, temperature dependent evaluation of leakage power of every active layer in a 3-D chip while taking the interlayer thermal couplings [5], [13] into account can be a key factor in determining the practical applicability of 3-D technology.…”

Section: Prior Literature and Scope Of This Workmentioning

confidence: 99%

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy

Loi¹,

Agrawal²,

Srivastava³

et al. 2006

2006 43rd ACM/IEEE Design Automation Conference

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Section: Prior Literature and Scope Of This Workmentioning

confidence: 99%

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy

Loi¹,

Agrawal²,

Srivastava³

et al. 2006

2006 43rd ACM/IEEE Design Automation Conference

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“…Many different uses of 3-D integration have been proposed, from stacking additional memory or extra levels of cache [10,34,43,24,47,20,19] to stacking multiple processors [6]. These two examples exploit the full advantages of 3-D chips, as attaching additional memory can provide lower latency compared to off-chip memory, and power can be saved because driving TSVs requires less power than long off-chip wires.…”

Section: Applications Of 3-d Integrationmentioning

confidence: 99%

A Qualitative Security Analysis of a New Class of 3-D Integrated Crypto Co-processors

Valamehr

Huffmire

Irvine

et al. 2012

Cryptography and Security: From Theory to Applications

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3-D integration presents many new opportunities for architects and embedded systems designers. However, 3-D integration has not yet been explored by the cryptographic hardware community. Traditionally, crypto coprocessors have been implemented as a separate die or by utilizing one or more cores in a chip multiprocessor. These methods have their drawbacks and limitations in terms of tamper-resistance, side-channel immunity and performance. In this work we propose a new class of co-processors that are "snapped-on" to the main processor using 3-D integration, and we investigate their security ramifications. These 3-D co-processors hold many advantages over previous implementations. This paper begins with an overview of 3-D integration and its prior applications. We then outline security threat models relevant to crypto co-processors and discuss the advantages and disadvantages of using a dedicated 3-D crypto co-processor compared to traditional, commodity, off-chip crypto co-processors. We also discuss the performance improvements that can be gained from using a 3-D approach.

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“…Several 3-D interconnect technologies are currently being evaluated in industry as a means of stacking multiple chips together. Some potential applications include the stacking of DRAM or bigger caches directly onto the processor die to alleviate memory pressure [17] and designing stacked chips of multiple processors [2]. Toshiba has applied 3-D integration to a CMOS image sensor camera module for mobile phones, which they call a Chip Scale Camera Module (CSCM), achieving a significant reduction in size while satisfying high-speed I/O requirements [24].…”

Section: -D Integrationmentioning

confidence: 99%

Hardware assistance for trustworthy systems through 3-D integration

Valamehr

Tiwari

Sherwood

et al. 2010

Proceedings of the 26th Annual Computer Security Applications Conference

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Hardware resources are abundant; state-of-the-art processors have over one billion transistors. Yet for a variety of reasons, specialized hardware functions for high assurance processing are seldom (i.e., a couple of features per vendor over twenty years) integrated into these commodity processors, despite a small flurry of late (e.g., ARM TrustZone, Intel VT-x/VT-d and AMD-V/AMD-Vi, Intel TXT and AMD SVM, and Intel AES-NI). Furthermore, as chips increase in complexity, trustworthy processing of sensitive information can become increasingly difficult to achieve due to extensive on-chip resource sharing and the lack of corresponding protection mechanisms. In this paper, we introduce a method to enhance the security of commodity integrated circuits, using minor modifications, in conjunction with a separate integrated circuit that can provide monitoring, access control, and other useful security functions. We introduce a new architecture using a separate control plane, stacked using 3-D integration, that allows for the function and economics of specialized security mechanisms, not available from a coprocessor alone, to be integrated with the underlying commodity computing hardware. We first describe a general methodology to modify the host computation plane by attaching an optional control plane using 3-D integration. In a developed example we show how this approach can increase Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ACSAC '10 Dec. 6-10, 2010, Austin, Texas USA Copyright 2010 ACM 978-1-4503-0133-6/10/12 ...$10.00. system trustworthiness, through mitigating the cache-based side channel problem by routing signals from the computation plane through a cache monitor in the 3-D control plane. We show that the overhead of our example application, in terms of area, delay and performance impact, is negligible.

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Self-Consistent Modeling of Heating and MOSFET Performance in 3-D Integrated Circuits

Cited by 41 publications

References 19 publications

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy

A Qualitative Security Analysis of a New Class of 3-D Integrated Crypto Co-processors

Hardware assistance for trustworthy systems through 3-D integration

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