Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?

Abstract

Quasi-Delay-Insensitive design is a promising solution for coping with contemporary silicon technology problems such as aggressive process variation and tight power budgets. However, one major barrier to its wider adoption is the lack of support for automated optimization techniques in semi-custom design flows. This paper proposes an innovative design flow that relies on the use of consolidated commercial EDA frameworks for synthesizing 1-of-n 4-phase Quasi-Delay-Insensitive circuits using Null Convention Logic. Accordingly, asynchronous gates, which are usually not supported by these frameworks, are modelled as conventional logic gates, allowing synthesis tools to perform static timing analysis and pre-and post-mapped design optimizations that can be specified by the designer using conventional timing constraints.

Snake: An asynchronous pipeline for ultra-low-power applications

“…The other is to provide compatibility with existing synchronous languages and EDA tools. [19,20,21] redesign asynchronous standard cell (ASTC) libraries in NCL [22] style. After synchronous synthesis, they translate the netlists to ASTC.…”

Asynchronous Design—Part 2: Systems and Methodologies

“…More recent NCL flows have made significant advances in automated CAD tool integration, support for semicustom asynchronous libraries, and hazardfree logic optimization and technology mapping. 22,23 Other Complete Design Flows. An integrated asynchronous synthesis flow from the startup company, Tiempo, uses highlevel Transaction Level Modeling (TLM), based on SystemVerilog, for specification entry.…”

Evolution of NULL Convention Logic Based Asynchronous Paradigm: An Overview and Outlook

“…This is because NCL threshold gates do not directly map to the conventional standard cell libraries as provided by commercial design automation frameworks. An emerging semi-custom design flow is proposed and discussed in detail in [37] to bridge this gap in technology mapping. The design flow has its own approach to technology mapping of a logic network, where a network, specified in VHDL/Verilog, is mapped to a limited set of NCL gates using the concept of Boolean Virtual Functions (BVFs).…”

“…An NCL Virtual Library is then generated from the Boolean netlist. It is at this point where the design flow in [37] starts to differ significantly from the other works from literature, in that it can use conventional CAD tools to adjust the mapped network on the circuit level to account for timing and power constraints. However, previous works (e.g., [23], [26], and [27]) extensively discussed and warned about the possibility of generating gate orphans during technology mapping and logic optimization using commercial CAD tools, which could potentially generate a corrupted netlist.…”

“…However, previous works (e.g., [23], [26], and [27]) extensively discussed and warned about the possibility of generating gate orphans during technology mapping and logic optimization using commercial CAD tools, which could potentially generate a corrupted netlist. [37] addresses and tackles the issue of corrupted netlist generation using a library of NCL+ gates, which is a variant of NCL gates, and is based on the authors' previous work [39]. Unlike NCL gates that use Return-to-Zero (RTZ) handshake protocol, NCL+ gates are designed to work with Return-to-One (RTO) handshake protocol [40].…”