Si–H Bond Breaking Induced Retention Degradation During Packaging Process of 256 Mbit DRAMs With Negative Wordline Bias

Chang, Minchen; Lin, Jengping; Lai, Chao−Sung; Chang, Ruey-Dar; Shih, Steven; Wang, Mao-Ying; Lee, P.-I.

doi:10.1109/ted.2005.844743

Cited by 27 publications

(12 citation statements)

References 16 publications

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“…When this trap becomes occupied, charge leaks more readily from the access transistor's drain (to which the cell's capacitor is connected). This process is therefore referred to as trap-assisted gate-induced drain leakage (TA-GIDL) [3].…”

Section: Dram Retention Time Profilingmentioning

confidence: 99%

“…Suppose a cell's retention time state changes due to VRT at one point during a round. 3 With all tests at a given t WAIT running together, in the worst case, the retention time changes between data patterns, resulting in an anomalous result for a single t WAIT . However, since the retention time state will still be consistent across data patterns for both the previous and next values of t WAIT , the change in observed retention time between data patterns should still be minimal (in the absence of DPD).…”

Section: Data Is Read Back From the Dram And Checked For Corruptionmentioning

confidence: 99%

“…These works established the key properties of VRT: the existence of multiple retention time states in VRT cells and the exponentially-distributed nature of the amount of time spent in each state. Since then, interest in VRT has focused on identifying its physical cause, primarily by measuring circuit-level features such as leakage currents [3,14,15,16,25,27,29]. No recent work we are aware of has evaluated the impact of VRT in modern DRAM devices.…”

Section: Variable Retention Timementioning

confidence: 99%

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An experimental study of data retention behavior in modern DRAM devices

LiuJamie

JaiyenBen

KimYoongu

et al. 2013

SIGARCH Comput. Archit. News

179

403

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DRAM cells store data in the form of charge on a capacitor. This charge leaks off over time, eventually causing data to be lost. To prevent this data loss from occurring, DRAM cells must be periodically refreshed. Unfortunately, DRAM refresh operations waste energy and also degrade system performance by interfering with memory requests. These problems are expected to worsen as DRAM density increases.The amount of time that a DRAM cell can safely retain data without being refreshed is called the cell's retention time. In current systems, all DRAM cells are refreshed at the rate required to guarantee the integrity of the cell with the shortest retention time, resulting in unnecessary refreshes for cells with longer retention times. Prior work has proposed to reduce unnecessary refreshes by exploiting differences in retention time among DRAM cells; however, such mechanisms require knowledge of each cell's retention time.In this paper, we present a comprehensive quantitative study of retention behavior in modern DRAMs. Using a temperaturecontrolled FPGA-based testing platform, we collect retention time information from 248 commodity DDR3 DRAM chips from five major DRAM vendors. We observe two significant phenomena: data pattern dependence, where the retention time of each DRAM cell is significantly affected by the data stored in other DRAM cells, and variable retention time, where the retention time of some DRAM cells changes unpredictably over time. We discuss possible physical explanations for these phenomena, how their magnitude may be affected by DRAM technology scaling, and their ramifications for DRAM retention time profiling mechanisms.

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Section: Dram Retention Time Profilingmentioning

confidence: 99%

Section: Data Is Read Back From the Dram And Checked For Corruptionmentioning

confidence: 99%

Section: Variable Retention Timementioning

confidence: 99%

See 1 more Smart Citation

An experimental study of data retention behavior in modern DRAM devices

LiuJamie

JaiyenBen

KimYoongu

et al. 2013

SIGARCH Comput. Archit. News

179

403

View full text Add to dashboard Cite

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“…As a result, the cell leaks faster and exhibits lower retention time. However, when the trap becomes empty again, the leakage current reduces, resulting in a higher retention time [7,20]. Depending on the amount of the leakage current, VRT cells exhibit different retention times.…”

Section: A Causes Of Vrtmentioning

confidence: 99%

AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems

Qureshi

Kim

Khan

et al. 2015

2015 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks

183

150

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Multirate refresh techniques exploit the nonuniformity in retention times of DRAM cells to reduce the DRAM refresh overheads. Such techniques rely on accurate profiling of retention times of cells, and perform faster refresh only for a few rows which have cells with low retention times. Unfortunately, retention times of some cells can change at runtime due to Variable Retention Time (VRT), which makes it impractical to reliably deploy multirate refresh.Based on experimental data from 24 DRAM chips, we develop architecture-level models for analyzing the impact of VRT. We show that simply relying on ECC DIMMs to correct VRT failures is unusable as it causes a data error once every few months. We propose AVATAR, a VRT-aware multirate refresh scheme that adaptively changes the refresh rate for different rows at runtime based on current VRT failures. AVATAR provides a time to failure in the regime of several tens of years while reducing refresh operations by 62%-72%.

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“…The data retention time characteristics are explained through monitoring the GIDL current and the interface-trap-density (D it ) by a charge pumping test. 6,7) 2. Fabrication Figure 2 represents 3D schematic illustration of key fabrication process of the body-tied S-Fin transistor.…”

Section: Introductionmentioning

confidence: 99%

Data Retention Characteristics for Gate Oxide Schemes in Sub-50 nm Saddle-Fin Transistor Dynamic-Random-Access-Memory Technology

Ryu¹,

Yoo²,

Choi

et al. 2011

Jpn. J. Appl. Phys.

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A data retention time has been investigated for various gate oxide schemes of saddle-fin (S-Fin) transistor dynamic random access memory (DRAM). The interface traps strongly affected the data retention time which was not clearly explained with a gate-induced-drain-leakage (GIDL) current as well as a junction leakage current. Despite the lower GIDL current by the thicker side-wall oxide of a dry oxidation scheme than a radical scheme, the degradation of the retention time was originated from the high interface-trap density (D it ). It is worthwhile to note that the D it as well as the GIDL current is a still meaning parameter to analyze the data retention time. #

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Si–H Bond Breaking Induced Retention Degradation During Packaging Process of 256 Mbit DRAMs With Negative Wordline Bias

Cited by 27 publications

References 16 publications

An experimental study of data retention behavior in modern DRAM devices

An experimental study of data retention behavior in modern DRAM devices

AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems

Data Retention Characteristics for Gate Oxide Schemes in Sub-50 nm Saddle-Fin Transistor Dynamic-Random-Access-Memory Technology

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