Silicon interposer technology for high-density package

Matsuo, M.; Hayasaka, N.; Okumura, Katsuya; Hosomi, E.; Takubo, C.

doi:10.1109/ectc.2000.853403

Cited by 29 publications

(13 citation statements)

References 2 publications

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“…The differential NEXT, at the output ports 5 and 6 is given by (11) for current mode drivers, and by (12) for voltage mode drivers…”

Section: Frequency Domain Modeling and Validationmentioning

confidence: 99%

“…Without considerable improvement in the performance and power of chip-to-chip interconnects, the boost in performance at the chip level cannot be translated to system-level improvements. Hence, many alternative technologies, including optical interconnects [5]- [7], 3-D-ICs [8]- [10], silicon interposers (SIs) [11]- [14], and air-gap interconnects [15]- [23], are being investigated. Optical interconnects have very little loss over long lengths, but due to the overhead of conversion to/from the electrical domain, they are mainly useful for longer interconnects at the backplane (BP) level in high performance servers and supercomputers [24].…”

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confidence: 99%

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Airgap Interconnects: Modeling, Optimization, and Benchmarking for Backplane, PCB, and Interposer Applications

Kumar

Sharma

Uzunlar

et al. 2014

IEEE Trans. Compon., Packag. Manufact. Technol.

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Frequency and time domain models are developed for backplane (BP), printed circuit board (PCB), and silicon interposer (SI) links using six-port transfer matrices (ABCD matrices) for bumps, vias and connectors, and coupled multiconductor transmission lines for traces. The six-port transfer matrix approach enables easy computation of the transfer function, as well as near-end and far-end crosstalk. The intersymbol interference is accounted for by computing the pulse response for the worst case bit pattern. Furthermore, the models developed here are used to optimize the data-rate and trace width for each of the links, so that the aggregate bandwidth obtained per joule of energy supplied to the link is maximized. The modeling and optimization approach developed here serves as a good platform to compare the air-gap interconnects against BP, PCB, and SI interconnects on lossy dielectrics. It is shown that air-gap interconnects can provide an aggregate bandwidth improvement of 3×-4× for BP links at a comparable energy per bit, and a 5×-9× improvement in aggregate bandwidth of PCB links at the expense of 20% higher energy per bit. For SI links, airgap interconnects are shown to provide a 2×-3× improvement in aggregate bandwidth and a 1×-1.5× improvement in energy per bit.Index Terms-Air-gap interconnects, chip-to-chip interconnects, data-rate and trace-width co-optimization, fine-pitch interconnects, silicon interposer (SI), time-domain modeling.

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“…The differential NEXT, at the output ports 5 and 6 is given by (11) for current mode drivers, and by (12) for voltage mode drivers…”

Section: Frequency Domain Modeling and Validationmentioning

confidence: 99%

mentioning

confidence: 99%

Airgap Interconnects: Modeling, Optimization, and Benchmarking for Backplane, PCB, and Interposer Applications

Kumar

Sharma

Uzunlar

et al. 2014

IEEE Trans. Compon., Packag. Manufact. Technol.

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“…Recently, there has been extensive research on the interposer based 2.5D technology [5][6] [10]. Some real products based on the 2.5D technology, such as Xilinx's virtex-7 FPGA, have already been commercialized [3].…”

Section: A Background Of 25d Technologymentioning

confidence: 99%

“…The conventional, low cost silicon interposer with wide bump pitch can be used in high density chips [5]. Recent research has pointed out that the TSV interposer is cost effective integrator for stacking integration [3].…”

Section: A Background Of 25d Technologymentioning

confidence: 99%

Fabrication cost analysis for 2D, 2.5D, and 3D IC designs

Zhang

Sun

2012

2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International

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The interposer-based 2.5D technology has some advantages that are provided in the 3D technology, such as low interconnect delay, and high bandwidth, etc. In addition, the 2.5D technology can mitigate area overhead of TSVs and help reduce the temperature and binding cost. An extra interposer layer, however, is introduced for interconnect in a 2.5D design. With 2D, 2.5D, and 3D design options, the fabrication cost is an important metric to decide which technology should be adopted for different designs. In this paper, we present a cost estimation method for 2.5D ICs by extending a 3D floorplanning tool and the 3D cost models. This method can provide an estimated cost comparison among three technologies as a reference of choosing the strategy during the early design stage. We apply our method to several design benchmarks and compare the cost with different design strategies. Moreover, the interconnect delay and temperature results are also provided for comparison.

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“…Moreover, silicon-based packaging process is inherently compatible with IC/MEMS (microelectro-mechanical system) processes, helping open up new opportunities for 3D heterogeneous integration. The siliconbased 3D integration, represented by silicon interposer technology, has been intensively researched recently (Matsuo et al, 2000;Zoschke et al, 2011;Limansyah et al, 2011;Kripesh et al, 2005). Most of the technologies have been developed for 3D IC integration, accommodating highdensity through-silicon vias (TSVs).…”

Section: Introductionmentioning

confidence: 99%

3D system-in-package design using stacked silicon submount technology

Santagata

Sokolovskij²,

Wei³

et al. 2015

Microelectronics International

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Purpose -This study aims to provide a flexible and cost-effective solution of 3D heterogeneous integration for applications such as micro-electro-mechanical system (MEMS) applications and smart sensor systems. Design/methodology/approach -A novel 3D system-in-package (SiP) based on stacked silicon submount technology was successfully developed and well-demonstrated by the fabrication and assembly process of a selected smart lighting module. Findings -The stacked module consists of multiple layers of silicon submounts which can be designed and fabricated in parallel. The bonding and interconnecting process is quite simple and does not require complicated equipment. The 3D stacking design offers higher silicon efficiency and miniaturized package form factor. The submount wafer can be assembled and tested at the wafer level, thus reducing the cost and improving the yield.Research limitations/implications -The embedding design presented in this paper is applicable for modules with limited number of passives. When it comes to cases with more passive devices, new process needs to be developed to achieve fast, inexpensive and reliable assembly. Originality/value -The presented 3D SiP design is novel for applications such as smart lighting, Internet of Things, MEMS systems, etc.

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Silicon interposer technology for high-density package

Cited by 29 publications

References 2 publications

Airgap Interconnects: Modeling, Optimization, and Benchmarking for Backplane, PCB, and Interposer Applications

Airgap Interconnects: Modeling, Optimization, and Benchmarking for Backplane, PCB, and Interposer Applications

Fabrication cost analysis for 2D, 2.5D, and 3D IC designs

3D system-in-package design using stacked silicon submount technology

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