Single-Event Tolerant Latch Using Cascode-Voltage Switch Logic Gates

Casey, Megan C.; Bhuva, B. L.; Black, J.D.; Massengill, L.W.; Amusan, O.A.; Witulski, A.F.

doi:10.1109/tns.2006.884970

Cited by 14 publications

(7 citation statements)

References 6 publications

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“…However, as circuit complexity increases, the double-exponential model overestimates the sensitivity to upsets, as evidenced by the CVSL results predicting nearly 50% more upsets over the bias-dependent model. In the case of the DICE circuit, the double exponential predicts upsets at far higher total charge for angled hits, whereas the bias-dependent model predicts upsets at far lower injected charges, as has been previously shown experimentally and in TCAD for this topology [12], [11]. Fig.…”

Section: Analysis For Upset: Comparison Of Observed Errors Based supporting

confidence: 65%

“…Methods have been proposed to model the interaction between adjacent devices during an ion strike, including mixed-mode simulation [11] as well as physics-based approaches including bipolar conduction [9]. While such approaches may be fundamentally valid, there are major shortcomings.…”

Section: Modeling Charge Sharing Behaviors For Ic Designmentioning

confidence: 99%

“…Thus, for this evaluation two common latch circuit topologies with RHBD redundancy were analyzed for charge sharing SET hardness, the DICE [15] and CVSL [11] latches, as illustrated in Figs. 4 and 5.…”

Section: Analysis For Upset: Comparison Of Observed Errors Based mentioning

confidence: 99%

“…The Cascode Voltage Switch Logic Latch replaces the two middle inverter stages of the DICE topology with CVSL NAND equivalents (Cells 1 and 2) for further RH improvement through addition of two extra redundant nodes (X4 and X5)[11].…”

mentioning

confidence: 99%

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Significance of Strike Model in Circuit-Level Prediction of Charge Sharing Upsets

Francis¹,

Dimitrov

Kauppila

et al. 2009

IEEE Trans. Nucl. Sci.

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When evaluating sub-100 nm circuits for hardness to Single Event Transients (SETs), the choice of strike model is shown to have a notable effect upon observed upsets. A method utilizing distributed charges to model strikes to adjacent devices is illustrated and utilized to compare the effect of strike kernel models in such Charge Sharing SETS (CSSETS). Bias-dependent models are shown to more accurately predict expected physical observations and Technology Computer Aided Design (TCAD) simulation, especially when such charge-sharing upsets must be considered.Index Terms-Charge sharing, radiation hardening by design (RHBD), radiation hardness assurance methodology, single event effects, single event transients (SETs).

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Section: Analysis For Upset: Comparison Of Observed Errors Based supporting

confidence: 65%

Section: Modeling Charge Sharing Behaviors For Ic Designmentioning

confidence: 99%

Section: Analysis For Upset: Comparison Of Observed Errors Based mentioning

confidence: 99%

mentioning

confidence: 99%

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Significance of Strike Model in Circuit-Level Prediction of Charge Sharing Upsets

Francis¹,

Dimitrov

Kauppila

et al. 2009

IEEE Trans. Nucl. Sci.

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“…For voltage perturbations smaller than the feedback delay, the cell may not upset. RHBD techniques to mitigate upsets in latches and memory increase the feedback delay time of the cell [4]- [7]. For example, one of the commonly used mitigation techniques for a static random access memory (SRAM) cell, composed of two cross-coupled inverters, is to increase the cell's feedback delay by adding resistance or capacitance [1].…”

Section: Multi-node Charge Collectionmentioning

confidence: 99%

Extended SET Pulses in Sequential Circuits Leading to Increased SE Vulnerability

Narasimham

Amusan

Bhuva

et al. 2008

IEEE Trans. Nucl. Sci.

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Mixed mode simulations and heavy-ion experiments indicate the presence of multi-node charge collection in advanced technologies. For logic circuits, such charge collection may result in concatenation of transients, extending the width of SETs. Mixedmode simulations of a 4-bit adder circuit indicate that the increase in SET pulse width due to two-node charge collection can be as high as 75%. An analytical model for the increase in the SET width is developed showing the increase in SET width is proportional to the width of the individual transients, the relative delay between charge collection nodes, and the circuit topology. Index Terms-Charge sharing, multi-node charge collection, pulse width, single event, single-event transient (SET).

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