SOI Flash Memory Scaling Limit and Design Consideration Based on 2-D Analytical Modeling

Nonvolatile Memory Cells Based on MoS2/Graphene Heterostructures

“…Vertical scaling leads to reduction of the program/erase voltages but is limited by the requirement of charge retention on the floating gate, which sets the limit for a minimum tunneling oxide thickness (∼5 nm). On the other hand, lateral scaling, driven by the quest for higher data storage capability, is seriously limited by the capacitive coupling between the drain electrode and the floating gate, which results in a longer penetration of the drain field in the transistor channel as the device is scaled. Furthermore, interference between neighboring cells leads to an undesirable spread in the threshold voltages of the devices .…”

Integration of High‐k Oxide on MoS2 by Using Ozone Pretreatment for High‐Performance MoS2 Top‐Gated Transistor with Thickness‐Dependent Carrier Scattering Investigation

“…In recent years, an extensive amount of studies has been conducted to explore 2D materials such as graphene and transition metal dichalcogenides (TMDs) for their unique structural features as well as outstanding electrical properties since their first discovery in 2004. Importantly, the atomic thickness makes them the better choices than traditional semiconductors at the device‐scaling limit, which is of great importance in circuit integration . Graphene has been demonstrated with the ultrahigh carrier mobility as a promising substitute for silicon.…”

Floating Gate Memory-based Monolayer MoS2Transistor with Metal Nanocrystals Embedded in the Gate Dielectrics

“…Generally, crystalline silicon is the dominant channel material used in the memory industry. As compared with silicon, monolayer MoS 2 has a relatively small dielectric constant (ε = 7) and atomic thickness, both of which can easily enable ultrathin‐body MOSFETs to suppress the short channel effect . Also, its comparably large device on/off ratio can facilitate the clear distinguishment between different memory states, being advantageous even for the multi‐level data storage .…”

“…This way, nonvolatile memory cells based on MoS 2 /graphene heterostructures were fabricated lately to tackle this issue . Employing this heterostructure, the capacitive interference between neighboring cells as well as the coupling between the electrodes and the floating gate can be significantly diminished through the minimization of the floating gate thickness . However, this sophisticated fabrication process would make it difficult for the commercial large‐scale production.…”