SOI high-voltage device with step thickness sustained voltage layer

IEEE Trans. Electron Devices

Yang

et al. 2019

An analytical model is proposed in this paper for optimizing the breakdown voltage (BV) and drift region doping concentration of a silicon-on-insulator (SOI) lateral power device with step width technique and high-k dielectric (SWHK device). By solving the 3-D Poisson equation, the analytical potential and the electric field distribution are investigated. The optimal width of the silicon region of each zone is calculated to obtain the maximum BV and optimal drift region doping concentration. The analytical results are well matched with the simulation results, confirming the validity of the present model. The proposed analytical model reveals the influence of step number and permittivity of high-k dielectric on the performances of the SWHK device and provides guidance for the optimal design of the SWHK device. Index Terms-Analytical model, breakdown voltage (BV), high-k, silicon-on-insulator (SOI), step width (SW). I. INTRODUCTION T HE silicon-on-insulator (SOI) lateral power device is widely used in intelligent power applications due to its high breakdown voltage (BV), high speed, small resistance, and reduced leakage current [1]-[5]. In order to improve the BV, an effective approach is to introduce several additional electric field peaks in the drift region, the structures including step doped (SD) drift region [6], [7], step thickness (ST) drift region [8], [9], step buried (SB) oxide layer [10], [11], and variable-k dielectric [12], [13]. With the proposal of Manuscript

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“…Solving the potential functions (6) and 7under the boundary conditions (8) and (9), the surface potential and electric field of each zone at x-direction along AA line are obtained as…”

Section: Analytical Model For the Electric Field And Verificationmentioning

confidence: 99%

Analytical Model for the SOI Lateral Power Device With Step Width Technique and High-${k}$ Dielectric

IEEE Trans. Electron Devices

Yang

et al. 2019

show abstract

“…An effective approach to improve the trade-off characteristics between the BV and R on,sp is to introduce several additional electric field peaks in the drift region. The structures include step doping (SD) [5,6] , step thickness (ST) [7,8] , buried oxide step structure (BOSS) [9,10] , step buried oxide interface charges (SBIC) [11] variable low-k dielectric buried layer and a buried p-layer (VLKD) [12] , and partial oxide pillar (POP) [13] . However, more masks would be required to fabricate the step doping SOI layer, the thickness SOI layer and step buried oxide layer, the process complexity and fabrication cost would increase.…”

Section: Introductionmentioning

confidence: 99%

Novel silicon-on-insulator lateral power device with step width drift region

Superlattices and Microstructures

Zhang

et al. 2015

“…Another effective approach to uniformizing the lateral electric field profile is to introduce several additional electric field peaks in the drift region. The typical structures include step doped (SD), 13,14) step thickness (ST), 15,16) buried oxide step structure (BOSS), 17) buried oxide double step (BODS), 18) step buried-oxide interface charges (SBIC), 19) variable low-k dielectric buried layer and a buried p-layer (VLKD), 20) and embedded p-type round pillars (EPRP). 21) In these structures, the BV increases with increasing number of additional electric field peaks, which means that more masks would be required to fabricate the step doped SOI layer, step thickness SOI layer, or step buried oxide layer.…”

Section: Introductionmentioning

confidence: 99%

Novel Silicon-on-Insulator Lateral Power Device with Partial Oxide Pillars in the Drift Region

Hua

et al. 2012

Jpn. J. Appl. Phys.